Software Configurable Multichannel Transceiver

Emerging test instrumentation and test scenarios increasingly require network communication to manage complexity. Adapting wireless communication infrastructure to accommodate challenging testing needs can benefit from reconfigurable radio technology. A fundamental requirement for a software-definable radio system is independence from carrier frequencies, one of the radio components that to date has seen only limited progress toward programmability. This paper overviews an ongoing project to validate the viability of a promising chipset that performs conversion of radio frequency (RF) signals directly into digital data for the wireless receiver and, for the transmitter, converts digital data into RF signals. The Software Configurable Multichannel Transceiver (SCMT) enables four transmitters and four receivers in a single unit the size of a commodity disk drive, programmable for any frequency band between 1 MHz and 6 GHz

Frequency Agile Transceiver for Advanced Vehicle Data Links

Emerging and next-generation test instrumentation increasingly relies on network communication to manage complex and dynamic test scenarios, particularly for uninhabited autonomous systems. Adapting wireless communication infrastructure to accommodate challenging testing needs can benefit from reconfigurable radio technology. Frequency agility is one characteristic of reconfigurable radios that to date has seen only limited progress toward programmability. This paper overviews an ongoing project to validate a promising chipset that performs conversion of RF signals directly into digital data for the wireless receiver and, for the transmitter, converts digital data into RF signals. The Software Configurable Multichannel Transceiver (SCMT) enables four transmitters and four receivers in a single unit, programmable for any frequency band between 1 MHz and 6 GHz

FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5G NR) communication systems. Simulation effort further increases when using more realistic geometry-based channel models, such as the three-dimensional spatial channel model (3D-SCM). Channel emulation is used for functional and performance verification of such models in the network planning phase. These models use multiple finite impulse response (FIR) filters and have a very high degree of parallelism which can be exploited for accelerated execution on Field Programmable Gate Array (FPGA) and Graphics Processing Unit (GPU) platforms. This paper proposes an efficient re-configurable implementation of the 3rd generation partnership project (3GPP) 3D-SCM on FPGAs using a design flow based on high-level synthesis (HLS). It studies the effect of various HLS optimization techniques on the total latency and hardware resource utilization on Xilinx Alveo U280 and Intel Arria 10GX 1150 high-performance FPGAs, using in both cases the commercial HLS tools of the producer. The channel model accuracy is preserved using double precision floating point arithmetic. This work analyzes in detail the effort to target the FPGA platforms using HLS tools, both in terms of common parallelization effort (shared by both FPGAs), and in terms of platform-specific effort, different for Xilinx and Intel FPGAs. Compared to the baseline general-purpose central processing unit (CPU) implementation, the achieved speedups are 65X and 95X using the Xilinx UltraScale+ and Intel Arria FPGA platform respectively, when using a Double Data Rate (DDR) memory interface. The FPGA-based designs also achieved ~3X better performance compared to a similar technology node NVIDIA GeForce GTX 1070 GPU, while consuming ~4X less energy. The FPGA implementation speedup improves up to 173X over the CPU baseline when using the Xilinx UltraRAM (URAM) and High-Bandwidth Memory (HBM) resources, also achieving 6X lower latency and 12X lower energy consumption than the GPU implementation

Automated test suite–a validation package for mobile chipsets

With the diminishing sizes of transistors, it is now possible to incorporate complex systems on a single die. The chipsets used in mobile phone handsets are a good example of such a complex systems. The design, validation, hardware development and software development of such complex chipsets is an intricate task which also consumes lot of time. With the increasing competition, time-to-market factor plays a crucial role in the development of a product. There is a constant need for an automated platform which would help designers at various stages in the development process of a complex product with minimum efforts. Automated Test Suite (ATS) is an automated Diagnostic Test System that enables the users to automate, validation procedures for any ADI DBB (ANALOG DEVICES digital base band) chipsets and H/W platforms in a user-friendly environment. This software follows the HostTarget model ensuring easy implementation of test cases so that the user can concentrate on the testing module only. It provides good modularity and reusability with simple structure. ATS has several features, these are: • Communication between Host and Target via RS232 or USB, • Usable with ANVIL evaluation boards • Remote execution of test routines on target from host. • Enables h/w platform testing – can be extended for performance and characterization testing. • Backwards and forwards extendable to other chipset families and h/w platforms. • Provides ‘Help’ feature for all the tests to user. • Script based testing ensures customizable test routine development. • Test result log - HTML based details and summary of test results • GUI based test tool gives user-friendly interface. Debug tools have been developed for some of the Hardware modules (LED, GPIO). This project was implemented in three phases. First phase includes the formulating of ATS architecture and provide sample implementation for LEMANS (AD6900 MSP 500) DBB. The second phase is adding new platform DIONE (AD6722 MSP 430) DBB to the existing ATS. Third phase concentrates on designing and implementing new ATS architecture for efficient performance and to reduce development time for ATS

View on 5G Architecture: Version 2.0

The 5G Architecture Working Group as part of the 5GPPP Initiative is looking at capturing novel trends and key technological enablers for the realization of the 5G architecture. It also targets at presenting in a harmonized way the architectural concepts developed in various projects and initiatives (not limited to 5GPPP projects only) so as to provide a consolidated view on the technical directions for the architecture design in the 5G era. The first version of the white paper was released in July 2016, which captured novel trends and key technological enablers for the realization of the 5G architecture vision along with harmonized architectural concepts from 5GPPP Phase 1 projects and initiatives. Capitalizing on the architectural vision and framework set by the first version of the white paper, this Version 2.0 of the white paper presents the latest findings and analyses with a particular focus on the concept evaluations, and accordingly it presents the consolidated overall architecture design

Software Defined Applications in Cellular and Optical Networks

abstract: Small wireless cells have the potential to overcome bottlenecks in wireless access through the sharing of spectrum resources. A novel access backhaul network architecture based on a Smart Gateway (Sm-GW) between the small cell base stations, e.g., LTE eNBs, and the conventional backhaul gateways, e.g., LTE Servicing/Packet Gateways (S/P-GWs) has been introduced to address the bottleneck. The Sm-GW flexibly schedules uplink transmissions for the eNBs. Based on software defined networking (SDN) a management mechanism that allows multiple operator to flexibly inter-operate via multiple Sm-GWs with a multitude of small cells has been proposed. This dissertation also comprehensively survey the studies that examine the SDN paradigm in optical networks. Along with the PHY functional split improvements, the performance of Distributed Converged Cable Access Platform (DCCAP) in the cable architectures especially for the Remote-PHY and Remote-MACPHY nodes has been evaluated. In the PHY functional split, in addition to the re-use of infrastructure with a common FFT module for multiple technologies, a novel cross functional split interaction to cache the repetitive QAM symbols across time at the remote node to reduce the transmission rate requirement of the fronthaul link has been proposed.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201