Analog Fault Identification in RF Circuits using Artificial Neural Networks and Constrained Parameter Extraction

The increase of analog and mixed-signal circuitry in modern RF and microwave integrated circuits demands for improved analog fault diagnosis methods. While digital fault diagnosis is well established, the analog counterpart is relatively much less mature due to the intrinsic complexity in analog faults and their corresponding identification. In this work, we present an artificial neural network (ANN) modeling approach to efficiently emulate the injection of analog faults in RF circuits. The resulting meta-model is used for fault identification by applying an optimization-based process using a constrained parameter extraction formulation. The proposed methodology is illustrated by a faulty analog CMOS RF circuit

Analog Gross Fault Identification in RF Circuits using Neural Models and Constrained Parameter Extraction

The demand and relevance of efficient analog fault diagnosis methods for modern RF and microwave integrated circuits increases with the growing need and complexity of analog and mixed-signal circuitry. The well-established digital fault diagnosis methods are insufficient for analog circuitry due to the intrinsic complexity in analog faults and their corresponding identification process. In this work, we present an artificial neural network (ANN) modeling approach to efficiently emulate the injection of analog faults in RF circuits. The resulting meta-model is used for fault identification by applying an optimization-based process using a constrained parameter extraction formulation. A generalized neural modeling formulation to include auxiliary measurements in the circuit is proposed. This generalized formulation significantly increases the uniqueness of the faults identification process. The proposed methodology is illustrated by two faulty analog circuits: a CMOS RF voltage amplifier and a reconfigurable bandpass microstrip filter

Assessing the effectiveness of different test approaches for power devices in a PCB

Power electronic systems employing Printed Circuit Boards (PCBs) are broadly used in many applications, including some safety-critical ones. Several standards (e.g., ISO26262 for the automotive sector and DO-178 for avionics) mandate the adoption of effective test procedures for all electronic systems. However, the metrics to be used to compute the effectiveness of the adopted test procedures are not so clearly defined for power devices and systems. In the last years, some commercial fault simulation tools (e.g., DefectSim by Mentor Graphics and TestMAX by Synopsys) for analog circuits have been introduced, together with some new fault models. With these new tools, systematic analog fault simulation finally became practically feasible. The aim of this paper is twofold: first, we propose a method to extend the usage of the new analog fault models to power devices, thus allowing to compute a Fault Coverage figure for a given test. Secondly, we adopt the method on a case study, for which we quantitatively evaluate the effectiveness of some test procedures commonly used at the PCB level for the detection of faults inside power devices. A typical Power Supply Unit (PSU) used in industrial products, including power transistors and power diodes, is considered. The analysis of the gathered results shows that using the new method we can identify the main points of strength / weakness of the different test solutions in a quantitative and deterministic manner, and pinpoint the faults escaping to each one

Reliability in Power Electronics and Power Systems

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