670 research outputs found
Fourier Domain Decoding Algorithm of Non-Binary LDPC codes for Parallel Implementation
For decoding non-binary low-density parity check (LDPC) codes,
logarithm-domain sum-product (Log-SP) algorithms were proposed for reducing
quantization effects of SP algorithm in conjunction with FFT. Since FFT is not
applicable in the logarithm domain, the computations required at check nodes in
the Log-SP algorithms are computationally intensive. What is worth, check nodes
usually have higher degree than variable nodes. As a result, most of the time
for decoding is used for check node computations, which leads to a bottleneck
effect. In this paper, we propose a Log-SP algorithm in the Fourier domain.
With this algorithm, the role of variable nodes and check nodes are switched.
The intensive computations are spread over lower-degree variable nodes, which
can be efficiently calculated in parallel. Furthermore, we develop a fast
calculation method for the estimated bits and syndromes in the Fourier domain.Comment: To appear in IEICE Trans. Fundamentals, vol.E93-A, no.11 November
201
MASSIVE PARALLEL DECODING OF LOW-DENSITY PARITY-CHECK CODES USING GRAPHIC CARDS
The belief propagation decoder for LDPS codes is ported to CUDATM and optimized for a high amount of parallel computation. The resulting implementation shall be compared with a non-parallel version on state-of-the-art PCs.Monzó Solves, E. (2010). MASSIVE PARALLEL DECODING OF LOW-DENSITY PARITY-CHECK CODES USING GRAPHIC CARDS. Universitat Politècnica de València. http://hdl.handle.net/10251/1373
An Iteratively Decodable Tensor Product Code with Application to Data Storage
The error pattern correcting code (EPCC) can be constructed to provide a
syndrome decoding table targeting the dominant error events of an inter-symbol
interference channel at the output of the Viterbi detector. For the size of the
syndrome table to be manageable and the list of possible error events to be
reasonable in size, the codeword length of EPCC needs to be short enough.
However, the rate of such a short length code will be too low for hard drive
applications. To accommodate the required large redundancy, it is possible to
record only a highly compressed function of the parity bits of EPCC's tensor
product with a symbol correcting code. In this paper, we show that the proposed
tensor error-pattern correcting code (T-EPCC) is linear time encodable and also
devise a low-complexity soft iterative decoding algorithm for EPCC's tensor
product with q-ary LDPC (T-EPCC-qLDPC). Simulation results show that
T-EPCC-qLDPC achieves almost similar performance to single-level qLDPC with a
1/2 KB sector at 50% reduction in decoding complexity. Moreover, 1 KB
T-EPCC-qLDPC surpasses the performance of 1/2 KB single-level qLDPC at the same
decoder complexity.Comment: Hakim Alhussien, Jaekyun Moon, "An Iteratively Decodable Tensor
Product Code with Application to Data Storage
Low-Density Arrays of Circulant Matrices: Rank and Row-Redundancy Analysis, and Quasi-Cyclic LDPC Codes
This paper is concerned with general analysis on the rank and row-redundancy
of an array of circulants whose null space defines a QC-LDPC code. Based on the
Fourier transform and the properties of conjugacy classes and Hadamard products
of matrices, we derive tight upper bounds on rank and row-redundancy for
general array of circulants, which make it possible to consider row-redundancy
in constructions of QC-LDPC codes to achieve better performance. We further
investigate the rank of two types of construction of QC-LDPC codes:
constructions based on Vandermonde Matrices and Latin Squares and give
combinatorial expression of the exact rank in some specific cases, which
demonstrates the tightness of the bound we derive. Moreover, several types of
new construction of QC-LDPC codes with large row-redundancy are presented and
analyzed.Comment: arXiv admin note: text overlap with arXiv:1004.118
A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes
Non-binary low-density parity-check codes are robust to various channel
impairments. However, based on the existing decoding algorithms, the decoder
implementations are expensive because of their excessive computational
complexity and memory usage. Based on the combinatorial optimization, we
present an approximation method for the check node processing. The simulation
results demonstrate that our scheme has small performance loss over the
additive white Gaussian noise channel and independent Rayleigh fading channel.
Furthermore, the proposed reduced-complexity realization provides significant
savings on hardware, so it yields a good performance-complexity tradeoff and
can be efficiently implemented.Comment: Partially presented in ICNC 2012, International Conference on
Computing, Networking and Communications. Accepted by IEEE Transactions on
Communication
Challenges and Some New Directions in Channel Coding
Three areas of ongoing research in channel coding are surveyed, and recent developments are presented in each area: spatially coupled Low-Density Parity-Check (LDPC) codes, nonbinary LDPC codes, and polar coding.This is the author accepted manuscript. The final version is available from IEEE via http://dx.doi.org/10.1109/JCN.2015.00006
Sub-graph based joint sparse graph for sparse code multiple access systems
Sparse code multiple access (SCMA) is a promising air interface candidate technique for next generation mobile networks, especially for massive machine type communications (mMTC). In this paper, we design a LDPC coded SCMA detector by combining the sparse graphs of LDPC and SCMA into one joint sparse graph (JSG). In our proposed scheme, SCMA sparse graph (SSG) defined by small size indicator matrix is utilized to construct the JSG, which is termed as sub-graph based joint sparse graph of SCMA (SG-JSG-SCMA). In this paper, we first study the binary-LDPC (B-LDPC) coded SGJSG- SCMA system. To combine the SCMA variable node (SVN) and LDPC variable node (LVN) into one joint variable node (JVN), a non-binary LDPC (NB-LDPC) coded SG-JSG-SCMA is also proposed. Furthermore, to reduce the complexity of NBLDPC coded SG-JSG-SCMA, a joint trellis representation (JTR) is introduced to represent the search space of NB-LDPC coded SG-JSG-SCMA. Based on JTR, a low complexity joint trellis based detection and decoding (JTDD) algorithm is proposed to reduce the computational complexity of NB-LDPC coded SGJSG- SCMA system. According to the simulation results, SG-JSGSCMA brings significant performance improvement compare to the conventional receiver using the disjoint approach, and it can also outperform a Turbo-structured receiver with comparable complexity. Moreover, the joint approach also has advantages in terms of processing latency compare to the Turbo approaches
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