Field solver technologies for variation-aware interconnect parasitic extraction

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 207-213).Advances in integrated circuit manufacturing technologies have enabled high density onchip integration by constantly scaling down the device and interconnect feature size. As a consequence of the ongoing technology scaling (from 45nm to 32nm, 22nm and beyond), geometrical variabilities induced by the uncertainties in the manufacturing processes are becoming more significant. Indeed, the dimensions and shapes of the manufactured devices and interconnect structures may vary by up to 40% from their design intent. The effect of such variabilities on the electrical characteristics of both devices and interconnects must be accurately evaluated and accounted for during the design phase. In the last few years, there have been several attempts to develop variation-aware extraction algorithms, i.e. algorithms that evaluate the effect of geometrical variabilities on the electrical characteristics of devices and interconnects. However, most algorithms remain computationally very expensive. In this thesis the focus is on variation-aware interconnect parasitic extraction. In the first part of the thesis several discretization-based variation-aware solver techniques are developed. The first technique is a stochastic model reduction algorithm (SMOR) The SMOR guarantees that the statistical moments computed from the reduced model are the same as those of the full model. The SMOR works best for problems in which the desired electrical property is contained in an easily defined subspace.(cont.) The second technique is the combined Neumann Hermite expansion (CNHE). The CNHE combines the advantages of both the standard Neumann expansion and the standard stochastic Galerkin method to produce a very efficient extraction algorithm. The CNHE works best in problems for which the desired electrical property (e.g. impedance) is accurately expanded in terms of a low order multivariate Hermite expansion. The third technique is the stochastic dominant singular vectors method (SDSV). The SDSV uses stochastic optimization in order to sequentially determine an optimal reduced subspace, in which the solution can be accurately represented. The SDSV works best for large dimensional problems, since its complexity is almost independent of the size of the parameter space. In the second part of the thesis, several novel discretization-free variation aware extraction techniques for both resistance and capacitance extraction are developed. First we present a variation-aware floating random walk (FRW) to extract the capacitance/resistance in the presence of non-topological (edge-defined) variations. The complexity of such algorithm is almost independent of the number of varying parameters. Then we introduce the Hierarchical FRW to extract the capacitance/resistance of a very large number of topologically different structures, which are all constructed from the same set of building blocks. The complexity of such algorithm is almost independent of the total number of structures. All the proposed techniques are applied to a variety of examples, showing orders of magnitude reduction in the computational time compared to the standard approaches. In addition, we solve very large dimensional examples that are intractable when using standard approaches.by Tarek Ali El-Moselhy.Ph.D

Integrated Electronics for Molecular Biosensing

This thesis, Integrated electronics for molecular biosensing, focuses on different approaches to sense the presence and activity of a specific analyte by using integrated electronic platforms. The aim of the first platform is to detect the enzyme telomerase. Telomerase causes the elongation of telomeres, which are part of the chromosomes, and determines the lifespan of cells. Telomerase expression is a marker of malignity in tumoral cells and its evaluation can be exploited for early diagnosis of many types of cancer cells. To detect the telomerase enzyme, a CMOS (complementary metal-oxide semiconductor) biosensor based on CMFET (Charge-Modulated Field Effect Transistor) able to measure kinetics of DNA replication and telomerase reaction was developed. The sensor can be functionalized by immobilizing single strands of DNA that contain the telomeric sequence, used as probes. If telomerase is present, the probes will be elongated by the enzyme and the charge on the sensing area will change, which reflects in a variation of the output current or voltage. The chip includes three different readout schemes (voltage, current- and time-based), each of which has different measuring ranges and operating conditions. The measured data is then digitized, stored, and can be sent off-chip through SPI (Serial Peripheral Interface) protocol. A total of 1024 biosensors have been integrated in a single chip with a size of 10x10 mm2. Each sensor can be independently addressed and functionalized by an electrochemical procedure using an integrated potentiostat, thus requiring no external equipment. Although the sensors have been tailored and optimized to perform telomerase detection, the sensing areas can be functionalized to be used with different analytes. This feature turns the chip into a complete bioassay platform. The second part of this work rises from the idea that bacteria, like Escherichia coli, can detect analytes in solution even at extremely low concentrations and change their movement through a process called chemotaxis, to move towards chemical gradients in the solution. E. coli moves by rotating its flagella either clockwise (for random tumbles) or counterclockwise (for straight runs, when it senses a chemical it is attracted to). Therefore, observing bacteria flagellar rotation can give enough information on the presence of a specific analyte in the solution. To electronically detect bacteria movement, an active surface covered in electrodes has been designed. By measuring the impedance between each pair of electrodes through an integrated LIA (lock-in amplifier), it is possible to know how a single bacterium is moving. By that, the presence or absence of the analyte can be deduced, thus effectively turning bacteria into chemical sensors

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Field-Effect Sensors

This Special Issue focuses on fundamental and applied research on different types of field-effect chemical sensors and biosensors. The topics include device concepts for field-effect sensors, their modeling, and theory as well as fabrication strategies. Field-effect sensors for biomedical analysis, food control, environmental monitoring, and the recording of neuronal and cell-based signals are discussed, among other factors

Development of a Macro-Pixel sensor for the Phase-2 Upgrade of the CMS experiment

No description available (migrated from EKP Invenio record 49080

Design techniques for high-performance current-steering digital-to-analog converters

Digital-to-Analog Converter (DAC) is a crucial building block limiting the accuracy and speed of many signal processing and telecommunication systems. To achieve high speed and high resolution, the current-steering architecture is almost exclusively used. Three important issues for current-steering DAC design are addressed in this dissertation. In a current-steering DAC design, it is essential that a designer determine the minimum required current source accuracy to overcome random current mismatch and achieve high linearity with guaranteed yield. Simple formulas are derived that clearly exhibit the relationship between the standard deviation of unit current sources, the bits of resolution, the INL/DNL, and the soft yield of DAC arrays. It is shown that these formulas are very effective for optimizing the DAC segmentation so as to achieve high performance and high yield with minimal area and power consumption. To overcome random mismatch effects without any trimming, the current source array of a high-accuracy DAC is usually rather large, causing the gradient errors in these arrays to become significant. How gradient errors affect the DAC linearity and how to compensate for them through switching sequence optimization is analyzed in the second part of this dissertation. To overcome technology barriers, relax the requirements on layout and reduce the sensitivities of DACs to process, temperature and aging, calibration is emerging as an attractive solution for the next-generation high-performance DACs, especially as process feature size keeps shrinking and supply voltage is reduced correspondingly. A new foreground calibration technique suitable for low-voltage environment is presented in the third part of this dissertation. It can effectively compensate for current source mismatches, and achieve high linearity with small die size and low power consumption. The dynamic performance of the DAC is also improved due to the dramatic reduction of parasitic effects. To demonstrate this technique, a 14-bit prototype was designed and fabricated in a 0.13u digital CMOS process. It is the first 14-bit CMOS DAC ever reported that operates with a single 1.5V power supply, occupies an active area less than 0.1mm2, and requires only 16.7mW at 100MHz sampling rate, but still maintains state-of-art linearity and speed

Integrated Circuits Parasitic Capacitance Extraction Using Machine Learning and its Application to Layout Optimization

The impact of parasitic elements on the overall circuit performance keeps increasing from one technology generation to the next. In advanced process nodes, the parasitic effects dominate the overall circuit performance. As a result, the accuracy requirements of parasitic extraction processes significantly increased, especially for parasitic capacitance extraction. Existing parasitic capacitance extraction tools face many challenges to cope with such new accuracy requirements that are set by semiconductor foundries (\u3c 5% error). Although field-solver methods can meet such requirements, they are very slow and have a limited capacity. The other alternative is the rule-based parasitic capacitance extraction methods, which are faster and have a high capacity; however, they cannot consistently provide good accuracy as they use a pre-characterized library of capacitance formulas that cover a limited number of layout patterns. On the other hand, the new parasitic extraction accuracy requirements also added more challenges on existing parasitic-aware routing optimization methods, where simplified parasitic models are used to optimize layouts. This dissertation provides new solutions for interconnect parasitic capacitance extraction and parasitic-aware routing optimization methodologies in order to cope with the new accuracy requirements of advanced process nodes as follows. First, machine learning compact models are developed in rule-based extractors to predict parasitic capacitances of cross-section layout patterns efficiently. The developed models mitigate the problems of the pre-characterized library approach, where each compact model is designed to extract parasitic capacitances of cross-sections of arbitrary distributed metal polygons that belong to a specific set of metal layers (i.e., layer combination) efficiently. Therefore, the number of covered layout patterns significantly increased. Second, machine learning compact models are developed to predict parasitic capacitances of middle-end-of-line (MEOL) layers around FINFETs and MOSFETs. Each compact model extracts parasitic capacitances of 3D MEOL patterns of a specific device type regardless of its metal polygons distribution. Therefore, the developed MEOL models can replace field-solvers in extracting MEOL patterns. Third, a novel accuracy-based hybrid parasitic capacitance extraction method is developed. The proposed hybrid flow divides a layout into windows and extracts the parasitic capacitances of each window using one of three parasitic capacitance extraction methods that include: 1) rule-based; 2) novel deep-neural-networks-based; and 3) field-solver methods. This hybrid methodology uses neural-networks classifiers to determine an appropriate extraction method for each window. Moreover, as an intermediate parasitic capacitance extraction method between rule-based and field-solver methods, a novel deep-neural-networks-based extraction method is developed. This intermediate level of accuracy and speed is needed since using only rule-based and field-solver methods (for hybrid extraction) results in using field-solver most of the time for any required high accuracy extraction. Eventually, a parasitic-aware layout routing optimization and analysis methodology is implemented based on an incremental parasitic extraction and a fast optimization methodology. Unlike existing flows that do not provide a mechanism to analyze the impact of modifying layout geometries on a circuit performance, the proposed methodology provides novel sensitivity circuit models to analyze the integrity of signals in layout routes. Such circuit models are based on an accurate matrix circuit representation, a cost function, and an accurate parasitic sensitivity extraction. The circuit models identify critical parasitic elements along with the corresponding layout geometries in a certain route, where they measure the sensitivity of a route’s performance to corresponding layout geometries very fast. Moreover, the proposed methodology uses a nonlinear programming technique to optimize problematic routes with pre-determined degrees of freedom using the proposed circuit models. Furthermore, it uses a novel incremental parasitic extraction method to extract parasitic elements of modified geometries efficiently, where the incremental extraction is used as a part of the routing optimization process to improve the optimization runtime and increase the optimization accuracy

Organic thin films: a comparison of their electrical and gas sensitivity

This thesis presents a study of the electrical properties and gas sensitivity of thin films of four different organic materials. These are: (i) Langmuir-Blodgett (LB) films of tetrabutylammonium Ni(dmit)(_2) complex (Bu(_4)-Ni(dmit)(_2) complex) mixed with tricosanoic acid (TA); (ii) thin films of polypyrrole (PPy) mixed with palmitic acid (PA) obtained using the LB technique followed by two solid state reactions; (iii) cast films of polycyanopropylmethylsiloxane (PCMS); and (iv) LB films of a co-ordination polymer?5,5' methylenebis (N-hexadecylsalicydeneamine) (MBSH) (poly(CuMBSH)). LB films of (Bu(_4)-Ni(dmit)(_2) complex)/TA were characterised by electrical measurements?(AC in the frequency range 10(^2)-10(^6) Hz) at room temperature. For the other three types of films, characterisation of the structure and electrical behaviour (DC and AC in the frequency range 10(^2)-10(^6) Hz) on varying the temperature (in the range 90 - 298 K) and during the exposure to benzene, ethanol, acetonitrile and water (concentrations in the range 10(^2) -10(^5) ppm) was undertaken. During exposure to vapours, reversible changes in the electrical properties of the films were observed. The electrical behaviour and the changes during exposure to vapours were interpreted in terms of models in the literature, assuming a bulk dissolution of the vapours in the organic films. In all cases an 'anomalous' response to water was observed. For poly(CuMBSH), this effect was interpreted in terras of a Low Frequency Dispersion. The device characteristics for gas sensing applications are also discussed. Estimated minimum detectable concentrations were between 1-100 ppm for the three organic solvent vapours. Moreover, it is shown that the fi-equency behaviour for the admittance changes of the PCMS and poly(CuMBSH) devices could be exploited for the improvement of the sensitivity of a single device. The unique response of all the films to water vapour could be useful for its discrimination

Design and commissioning of an experiment for sympathetic cooling and coupling of ions in a cryogenic Penning trap

Precise comparisons between the properties of matter and antimatter conjugates constitute a stringent test of CPT and Lorentz symmetries. The proton’s and antiproton’s magnetic moments have recently been measured to high precision in Penning traps, but further progress is impaired by the need to prepare a particle with low motional energy. Current preparation schemes require long preparation times and are limited by high temperatures. Sympathetic laser cooling using an atomic ion has been proposed for preparation of low-energy protons and antipro- tons. This thesis presents the design and commissioning of a cryogenic Penning trap system for sympathetic laser cooling using beryllium ions. The experiment aims to demonstrate direct Coulomb coupling between two particles trapped in nearby, but separate potential wells in a Penning trap stack for the first time. This technique could be used for sympathetic cooling of particles lacking the necessary substructure to apply laser cooling directly. The application of this method on protons and antiprotons has the potential to decrease the mean kinetic energies of the particles and the preparation times required by several orders of magnitude. Furthermore, the method can be extended to other particles, such as highly charged ions. A quantum logic spectroscopy scheme for the measurement of the magnetic moment of the proton and antiproton has been proposed by Heinzen and Wineland. Experimental requirements for realisation of this proposal are discussed. The design of a suitable Penning trap system is described. A cryogenic ultra-high vacuum system cooled by a closed-cycle cryocooler, equipped with an ultra low vibration interface, is designed and commissioned. The necessary infrastructure, such as laser systems and electronics are described. First signals taken from this newly constructed cryogenic Penning trap are presented. Laser ablation trap loading, Doppler cooling and the reduction of the particle number down to a single ion are demonstrated. Prospects of the experiment and implications for the precision of future measurements of the proton’s and antiproton’s magnetic moments augmented by sympathetic laser cooling and elements of quantum logic are discussed