A study of real-time computer graphic display technology for aeronautical applications

Hardware, algorithms and software for real-time raster graphics were designed and implemented

Learning to Program with Natural Language

Large Language Models (LLMs) have shown remarkable performance in various basic natural language tasks, which raises hope for achieving Artificial General Intelligence. For completing the complex task, we still need a program for the task first and then ask LLMs to follow the program to generate the specific solution. We propose using natural language as a new programming language to describe task procedures, making them easily understandable to both humans and LLMs. ~The LLM is capable of directly generating natural language programs, but these programs may still contain factual errors or incomplete steps. Therefore, we further propose the Learning to Program (\text{LP}) method to ask LLMs themselves to learn the natural language program based on the training dataset of the complex task first and then use the learned program to guide the inference. Our experiments on the reasoning tasks of five different reasoning types (8 datasets) demonstrate the effectiveness of our approach. Further, our analysis experiment shows that the learned program can be directly used to guide another LLM to improve its performance, which reveals a new transfer learning paradigm.Comment: Work in progres

FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders

Nowadays, the requirement for very high-speed operations in processors constantly increases. Multiplication is a crucial operation in high power-consuming processes such as image and signal processing. The main characteristics of a multiplier are good accuracy, speed, reduction in area, and little power consumption. Speed plays a major role in multiplication operations, and an increase in speed can be obtained by reducing the number of steps involved in the computation process. Since a multiplier has the largest delay among the basic blocks in a digital system, the critical path is determined by it. Furthermore, the multiplier consumes more area and dissipates more power. Hence, designing multipliers that offer high speed, lower power consumption, less area, or a combination of them is of prime concern. Hence, an attempt is made in this paper to achieve the above design metrics using a Spurious Power Suppression Technique (SPST) adder. A resource-efficient SPST-based Vedic multiplier is developed and implemented using Artix 7 FPGA and is finally compared with the ripple carry adder-based Vedic multiplier

Field Programmable Gate Arrays (FPGAs) II

This Edited Volume Field Programmable Gate Arrays (FPGAs) II is a collection of reviewed and relevant research chapters, offering a comprehensive overview of recent developments in the field of Computer and Information Science. The book comprises single chapters authored by various researchers and edited by an expert active in the Computer and Information Science research area. All chapters are complete in itself but united under a common research study topic. This publication aims at providing a thorough overview of the latest research efforts by international authors on Computer and Information Science, and open new possible research paths for further novel developments