Computational Prototyping Tools and Techniques

Contains reports on five research projects.Industry Consortium (Mobil, Statoil, DNV Software, Shell, OTRC, Petrobras, NorskHydro, Exxon, Chevron, SAGA, NSWC)U.S. Navy - Office of Naval ResearchAnalog DevicesDefense Advanced Research Projects Agency Contract J-FBI-95-215Cadence Design SystemsHarris SemiconductorMAFET ConsortiumMotorola SemiconductorDefense Advanced Research Projects AgencyMultiuniversity Research InitiativeSemiconductor Research CorporationIBM Corporatio

Custom Integrated Circuits

Contains table of contents for Part III, table of contents for Section 1 and reports on eleven research projects.IBM CorporationMIT School of EngineeringNational Science Foundation Grant MIP 94-23221Defense Advanced Research Projects Agency/U.S. Army Intelligence Center Contract DABT63-94-C-0053Mitsubishi CorporationNational Science Foundation Young Investigator Award Fellowship MIP 92-58376Joint Industry Program on Offshore Structure AnalysisAnalog DevicesDefense Advanced Research Projects AgencyCadence Design SystemsMAFET ConsortiumConsortium for Superconducting ElectronicsNational Defense Science and Engineering Graduate FellowshipDigital Equipment CorporationMIT Lincoln LaboratorySemiconductor Research CorporationMultiuniversity Research IntiativeNational Science Foundatio

Fast Numerical Model of Power Busbar Conductors Through the FFT and the Convolution Theorem

[EN] Skin and proximity effects can cause a non-uniform current distribution in the electrical conductors used in alternating current (ac) busbar systems, which increases resistance, decreases internal inductance, and causes asymmetries in the electromagnetic fields and forces. As no explicit solution for the ac resistance or the ac internal inductance of a rectangular conductor has been found, numerical methods are needed to obtain the distribution of the currents inside the busbars. In this paper, a novel numerical approach, based on the fast Fourier transform (FFT) and the convolution theorem, is proposed to model the rectangular conductors of the busbar system, based on the subdivision of the conductor in filamentary subconductors. This technique is know to lead to a dense, huge inductance matrix, that must be multiplied by the current vector, which limits its practical application. The proposed method replaces this matrix-vector multiplication with a simple element-wise vector product in the spatial frequency domain. The FFT speed makes the proposed method very fast and easy to apply. This approach is theoretically explained and applied to an industrial busbar system.This work was supported in part by the Spanish Ministerio de Ciencia, Innovación y Universidades (MCIU), in part by the Agencia Estatal de Investigación (AEI), and in part by the Fondo Europeo de Desarrollo Regional (FEDER) in the framework of the Proyectos I+D+i - Retos Investigación 2018, under Project Reference RTI2018-102175-B-I00 (MCIU/AEI/FEDER, UE).Martinez-Roman, J.; Puche-Panadero, R.; Sapena-Bano, A.; Burriel-Valencia, J.; Terrón-Santiago, C.; Pineda-Sanchez, M.; Riera-Guasp, M. (2022). Fast Numerical Model of Power Busbar Conductors Through the FFT and the Convolution Theorem. IEEE Transactions on Power Delivery. 37(4):1-11. https://doi.org/10.1109/TPWRD.2021.312626511137

Fast Algorithms for High Frequency Interconnect Modeling in VLSI Circuits and Packages

Interconnect modeling plays an important role in design and verification of VLSI circuits and packages. For low frequency circuits, great advances for parasitic resistance and capacitance extraction have been achieved and wide varieties of techniques are available. However, for high frequency circuits and packages, parasitic inductance and impedance extraction still poses a tremendous challenge. Existing algorithms, such as FastImp and FastHenry developed by MIT, are slow and inherently unable to handle multiple dielectrics and magnetic materials. In this research, we solve three problems in interconnect modeling for high frequency circuits and packages. 1) Multiple dielectrics are common in integrated circuits and packages. We propose the first Boundary Element Method (BEM) algorithm for impedance extraction of interconnects with multiple dielectrics. The algorithm uses a novel equivalentcharge formulation to model the extraction problem with significantly fewer unknowns. Then fast matrix-vector multiplication and effective preconditioning techniques are applied to speed up the solution of linear systems. Experimental results show that the algorithm is significantly faster than existing methods with sufficient accuracy. 2) Magnetic materials are widely used in MEMS, RFID and MRAM. We present the first BEM algorithm to extract interconnect inductance with magnetic materials. The algorithm models magnetic characteristics by the Landau Lifshitz Gilbert equation and fictitious magnetic charges. The algorithm is accelerated by approximating magnetic charge effects and by modeling currents with solenoidal basis. The relative error of the algorithm with respect to the commercial tool is below 3%, while the speed is up to one magnitude faster. 3) Since traditional interconnect model includes mutual inductances between pairs of segments, the resulting circuit matrix is very dense. This has been the main bottleneck in the use of the interconnect model. Recently, K = L-1 is used. The RKC model is sparse and stable. We study the practical issues of the RKC model. We validate the RKC model and propose an efficient way to achieve high accuracy extraction by circuit simulations of practical examples

Overview of Large-Scale Computing: The Past, the Present, and the Future

published_or_final_versio

Full-wave analysis of large conductor systems over substrate

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (leaves 137-145).Designers of high-performance integrated circuits are paying ever-increasing attention to minimizing problems associated with interconnects such as noise, signal delay, crosstalk, etc., many of which are caused by the presence of a conductive substrate. The severity of these problems increases as integrated circuit clock frequencies rise into the multiple gigahertz range. In this thesis, a simulation tool is presented for the extraction of full-wave interconnect impedances in the presence of a conducting substrate. The substrate effects are accounted for through the use of full-wave layered Green's functions in a mixed-potential integral equation (MPIE) formulation. Particularly, the choice of implementation for the layered Green's function kernels motivates the development of accelerated techniques for both their 3D volume and 2D surface integrations, where each integration type can be reduced to a sum of D line integrals. In addition, a set of high-order, frequency-independent basis functions is developed with the ability to parameterize the frequency-dependent nature of the solution space, hence reducing the number of unknowns required to capture the interconnects' frequency-variant behavior.(cont.) Moreover, a pre-corrected FFT acceleration technique, conventional for the treatment of scalar Green's function kernels, is extended in the solver to accommodate the dyadic Green's function kernels encountered in the substrate modeling problem. Overall, the integral-equation solver, combined with its numerous acceleration techniques, serves as a viable solution to full-wave substrate impedance extractions of large and complex interconnect structures.by Xin Hu.Ph.D

Tensor Computation: A New Framework for High-Dimensional Problems in EDA

Many critical EDA problems suffer from the curse of dimensionality, i.e. the very fast-scaling computational burden produced by large number of parameters and/or unknown variables. This phenomenon may be caused by multiple spatial or temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit simulation), nonlinearity of devices and circuits, large number of design or optimization parameters (e.g. full-chip routing/placement and circuit sizing), or extensive process variations (e.g. variability/reliability analysis and design for manufacturability). The computational challenges generated by such high dimensional problems are generally hard to handle efficiently with traditional EDA core algorithms that are based on matrix and vector computation. This paper presents "tensor computation" as an alternative general framework for the development of efficient EDA algorithms and tools. A tensor is a high-dimensional generalization of a matrix and a vector, and is a natural choice for both storing and solving efficiently high-dimensional EDA problems. This paper gives a basic tutorial on tensors, demonstrates some recent examples of EDA applications (e.g., nonlinear circuit modeling and high-dimensional uncertainty quantification), and suggests further open EDA problems where the use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and System

Rapid solution of potential integral equations in complicated 3-dimensional geometries

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (p. 133-137).by Joel Reuben Phillips.Ph.D