Спецпроцесори для двовимірного дискретного косинусного перетворення

Описано хід розробки спецпроцесорів для прямого і оберненого двовимірного дискретного косинусного перетворення з використанням метода синтезу конвеєрних обчислювальних пристроїв. Показані переваги цих процесорів як за швидкодією, так і за апаратними витратами при їхній реалізації в програмованих логічних інтегральних схемах.The process of development of 2-d DCT and IDCT processors using the method of pipeline processor synthesis is described. The advantages of these processors both due to its speed and due to its hardware volume by their implementation in FPGA are proven

A low multiplicative complexity fast recursive DCT-2 algorithm

A fast Discrete Cosine Transform (DCT) algorithm is introduced that can be of particular interest in image processing. The main features of the algorithm are regularity of the graph and very low arithmetic complexity. The 16-point version of the algorithm requires only 32 multiplications and 81 additions. The computational core of the algorithm consists of only 17 nontrivial multiplications, the rest 15 are scaling factors that can be compensated in the post-processing. The derivation of the algorithm is based on the algebraic signal processing theory (ASP).Comment: 4 pages, 2 figure

A Lossless Image Compression using Modified Entropy Coding

Due to size limitation and complexity of the hardware in transmission applications, multimedia systems and computer communications, compression techniques are much necessary. The reasons for multimedia systems to compress the data, large storage is required to save the compressed data, the storage devices are relatively slow which in real-time, has constrain to play multimedia data, and the network bandwidth, that has limitations to real-time data transmission. This paper presents an enhanced approach of run length coding. First the DCT applied, and the quantization done on the image to be compressed, then the modified run length coding technique has been used to compress the image losslessly. This scheme represents the occurrence of repeated zeros by RUN, and a non-zero coefficient by LEVEL. It removes the value of RUN, as for the sequence of non-zero coefficients it is zero for most of the time and for a zero present between non-zero coefficients is replaced by ‘0’ which results in larger compression than RUN, LEVEL (1, 0) pair is used

DELAY EFFICIENT ACT MODULE IMPLEMENTATION USING VLSI ARITHMETIC CIRCUITS

Lately, an arithmetic transform way of the computation from the DCT, known as the arithmetic cosine transform was suggested. However, the requirement of non-uniform samples could be satisfied when spatial input signals are thought. Particularly, the eight-point DCT and it is variants, by means of fast algorithms, continues to be broadly adopted in a number of image and video coding standards for example JPEG, MPEG-1/2, and H.261-5. The typical percentage error and PSNR were adopted as figures of merit to evaluate the measured results. It's the initial step towards new information on low power and occasional complexity computation from the DCT by way of the lately suggested ACT. We advise Architecture II that implements the novel modified ACT formula for DCT calculation of arbitrary, non-null-mean input signals, using 11 hardware multiplications. Both architectures require only non-uniformly sampled inputs. The designs are fully pipelined by cautious insertion of registers at internal nodes, resulting in low critical path delay at the expense of latency. The decrease in the input word-length L degrades the outcomes provided by the considered figures of merit. However, for small word-lengths, the errors incurred are tolerable for many applications. Precision from the is a result of Architectures I and II were tested with different values of L by utilizing average percentage error and peak signal to noise ratio as figures of merit. Adopted figures of merit employed the DCT coefficients calculated in the floating point implementation from the DCT obtainable in Matlab as reference

СИНТЕЗ FPGA-АРХИТЕКТУР БАНКОВ ФИЛЬТРОВ НА ОСНОВЕ БЛОЧНОЙ ЛЕСТНИЧНОЙ ФАКТОРИЗАЦИИ В АЛГЕБРЕ КВАТЕРНИОНОВ (ЧАСТЬ 1)

Nowadays the methodology for designing systems on a chip is based on highly parameterized IP components which provide a wide range of adjustment of costs in resources, fixed point arithmetic data formats and system performance for a specific target application. The article presents a systematic approach for synthesizing FPGA architectures of integer reversible paraunitary filter banks in quaternion algebra (Int-Q-PUBB) for L2L (lossless-to-lossy) image transformed encoding. It is shown that the basic elementary transformation of the filter bank is the operation of quaternion multiplication (Q-MUL), the block-lifting factorization of which and the distributed arithmetic on the adder are the basis of the parametrizable Q-MUL IP-component.В настоящее время методологии проектирования систем на кристалле основываются на высокопараметризированных IP-компонентах (IP – intellectual property), которые для конкретного целевого приложения обеспечивают широкий диапазон регулировки затрат ресурсов, форматов данных арифметики с фиксированной запятой и производительности системы. В статье представлен систематический подход к синтезу FPGA-архитектур целочисленных обратимых параунитарных банков фильтров в алгебре кватернионов (Int-Q-ПУБФ) для трансформационного кодирования изображений по схеме L2L (lossless-to-lossy). Показывается, что базовым элементарным преобразованием банка фильтров является операция умножения кватернионов (Q-MUL). Блочная лестничная факторизация данной операции и распределенная арифметика на сумматорах положены в основу параметризируемого Q-MUL IP-компонента

Проектирование процессора вычисления дискретного косинусного преобразования для систем сжатия изображения по схеме losless-to-lossy

Today, mobile multimedia systems that use the H.261 / 3/4/5, MPEG-1/2/4 and JPEG standards for encoding / decoding video, audio and images are widely spread [1–4]. The core of these standards is the discrete cosine  transform  (DCT)  of  I,  II,  III  ...  VIII  types  [DCT].  Wide support  in  a  huge  number  of  multimedia applications of the JPEG format by circuitry and software solutions and the need for image coding according to the  L2L  scheme  determines  the  relevance  of  the  problem  of  creating  a  decorrelated  transformation  based  on DCT and methods for rapid prototyping of processors for computing an integer DCT on programmable systems on a FPGA chip. At the same time, such characteristics as structural regularity, modularity, high computational parallelism,  low  latency  and  power  consumption  are  taken  into  account.  Direct  and  inverse  transformation should be carried out according to the “whole-to-whole” processing scheme with preservation of the perfective reconstruction  of  the  original  image  (the  coefficients  are  represented  by  integer  or  binary  rational  numbers; the number of multiplication operations is minimal, if possible, they are excluded from the algorithm). The wellknown  integer  DCTs  (BinDCT,  IntDCT)  do  not  give  a  complete  reversible  bit  to  bit  conversion.  To  encode an image  according  to  the  L2L  scheme,  the  decorrelated  transform must be reversible and implemented in integer  arithmetic,  i. e.  the  conversion  would  follow  an  “integer-to-integer”  processing  scheme  with  a minimum  number  of  rounding  operations  affecting  the  compactness of  energy  in  equivalent  conversion subbands. This article shows how, on the basis of integer forward and inverse DCTs, to create a new universal architecture of decorrelated transform on FPGAs for transformational image coding systems that operate on the principle of “lossless-to-lossy” (L2L), and to obtain the best experimental results for objective and subjective performance compared to comparable compression systems.На  сегодняшний  день  широко  распространены  мобильные  мультимедийные  системы, которые используют стандарты H.261/3/4/5, MPEG-1/2/4 и JPEG длякодирования/декодирования видео, аудио и изображений [1–4]. Ядром этих стандартов является дискретное косинусное преобразование (ДКП) I, II, III … VIII типов [ДКП]. Широкая поддержка в огромном количестве мультимедийных приложений формата  JPEG  схемотехническими и  программными  решениями  и  необходимость  кодирования изображений  по  схеме  L2L  обусловливает  актуальность  проблемы  создания  декоррелирующего преобразования  на  основе  ДКП  и  методов  быстрого  прототипирования  процессоров  вычисления целочисленного ДКП на программируемых системах на кристалле ПЛИС/FPGA. При этом во внимание принимаются  такие  характеристики,  как  структурная  регулярность, модульность,  высокий вычислительный  параллелизм,  малая  латентность  и потребляемая  мощность.  Прямое  и  обратное преобразования  должны  осуществляться  по  схеме  обработки  «целое к  целому»  с  сохранением перфективной  реконструкции  исходного  изображения  (коэффициенты представляются  целыми  или двоичными  рациональными  числами;  число  операций  умножения  минимально,  по  возможности  они исключаются  из  алгоритма).  Известные  целочисленные  ДКП  (BinDCT,IntDCT) не дают полного обратимого  бит  в  бит  преобразования.  Для  кодирования  изображения  по  схеме  L2L  требуется,  чтобы декоррелирующее  преобразование  было  обратимым  и  реализовано  в  целочисленной  арифметике, т. е.  преобразование  соответствовало  бы  схеме  обработки  «целое-в-целое»  при  минимальном  числе операций округления, влияющих на компактность энергии в эквивалентных субполосах преобразования. В  данной  статье  показано,  как  на основе  целочисленного  прямого и  обратного  ДКП  создать  новую универсальную  архитектуру  декоррелирующего  преобразования  на  ПЛИС типа FPGA для систем трансформационного кодирования изображений, которые работают попринципу lossless-to-lossy (L2L), и  получить  лучшие  экспериментальные  результаты  по  объективным  и субъективным  показателям по сравнению с аналогичными системами сжатия

Focal-Plane Change Triggered Video Compression for Low-Power Vision Sensor Systems

Video sensors with embedded compression offer significant energy savings in transmission but incur energy losses in the complexity of the encoder. Energy efficient video compression architectures for CMOS image sensors with focal-plane change detection are presented and analyzed. The compression architectures use pixel-level computational circuits to minimize energy usage by selectively processing only pixels which generate significant temporal intensity changes. Using the temporal intensity change detection to gate the operation of a differential DCT based encoder achieves nearly identical image quality to traditional systems (4dB decrease in PSNR) while reducing the amount of data that is processed by 67% and reducing overall power consumption reduction of 51%. These typical energy savings, resulting from the sparsity of motion activity in the visual scene, demonstrate the utility of focal-plane change triggered compression to surveillance vision systems

Arquitectura de Alto Rendimiento para el Cálculo de la DCT

En este trabajo se han revisado los principales métodos de cálculo de la Transformada Discreta del Coseno y sus implementaciones. A partir de esta información se ha propuesto una arquitectura de cálculo de alto rendimiento que pone en práctica técnicas de aritmética de computadores en el desarrollo de operadores para crear una estructura compacta que calcula la transformada a partir de su formulación directa. Se ha implementado y simulado el funcionamiento de la arquitectura propuesta en tarjetas reconfigurables para el Procesamiento de señales digitales, para evaluar su rendimiento en términos de área, retardo y potencia consumida. Además, se ha calculado su rendimiento con un modelo homogéneo e independiente de la tecnología de implementación con el propósito de comparar sus prestaciones con las de otras técnicas conocidas

Dynamic S-Box and PWLCM-Based Robust Watermarking Scheme

Due to the increased number of cyberattacks, numerous researchers are motivated towards the design of such schemes that can hide digital information in a signal. Watermarking is one of the promising technologies that can protect digital information. However, traditional watermarking schemes are either slow or less secure. In this paper, a dynamic S-Box based efficient watermarking scheme is presented. The original image was extracted at the receiver’s end without any loss of sensitive information. Firstly, the Secure Hash Algorithm is applied to the original image for the generation of the initial condition. Piece Wise Linear Chaotic Map is then used to generate 16 × 16 dynamic Substitution Box (S-Box). As an additional security feature, the watermark is substituted through dynamic S-Box. Hence, it is hard for the eavesdroppers to attack the proposed scheme due to the dynamic nature of S-Box. Lastly, lifting wavelet transform is applied to the host image and the High Low and High High blocks of host image are replaced with least significant bits and most significant bits of the substituted watermark, respectively. Robustness, efficiency and security of the proposed scheme is verified using Structure Similarity Index, Structure Dissimilarity Index, Structure Content, Mutual Information, energy, entropy, correlation tests and classical attacks analysis