A Novel Adaptive Search Range Algorithm for Motion Estimation Based on H.264

Motion estimation (ME) is very vital to video compression. Due to the adoption of the high precision of motion vector (MV) in H.264 encoder, the computational cost increases rapidly, and ME takes about 60% of the whole encoding time. In order to accommodate the new variable block size motion estimation strategy adopted in H.264, this paper proposes a novel adaptive search range(ASR) algorithm as a optimized part based on UMHexagonS. Not only we utilize the median_MVP and interframe information in our ASR algorithm but also a penalty function is included. Experimental results indicate that our proposed method reduces the computational complexity in a certain degree and enhances encoding efficiency but has few changes in the reconstructed image quality and bit rate

Block Matching Algorithms for the Estimation of Motion in Image Sequences: Analysis

Several video coding standards and techniques have been introduced for multimedia applications, particularly the h.26x series for video processing. These standards employ motion estimation processing to reduce the amount of data that is required to store or transmit the video. The motion estimation process is an inextricable part of the video coding as it removes the temporal redundancy between successive frames of video sequences. This paper is about these motion estimation algorithms, their search procedures, complexity, advantages, and limitations. A survey of motion estimation algorithms including full search, many fast, and fast full search block-based algorithms has been presented. An evaluation of up-to-date motion estimation algorithms, based on several empirical results on several test video sequences, is presented as well

Fast motion estimation algorithm in H.264 standard

In H.264/AVC standard, the block motion estimation pattern is used to estimate the motion which is a very time consuming part. Although many fast algorithms have been proposed to reduce the huge calculation, the motion estimation time still cannot achieve the critical real time application. So to develop an algorithm which will be fast and having low complexity became a challenge in this standard.For this reasons, a lot of block motion estimation algorithms have been proposed. Typically the block motion estimation part is categorized into two parts. (1) Single pixel motion estimation (2) Fractional pixel motion estimation. In single pixel motion estimation one kind of fast motion algorithm uses fixed pattern like Three Step search, 2-D Logarithmic Search. Four Step search,Diamond Search, Hexagon Based Search. These algorithms are able to reduce the search point and get good coding quality. But the coding quality decreases when the fixed pattern does not fit the real life video sequence. In this thesis we tried to reduce the time complexity and number of search point by using an early termination method which is called adaptive threshold selection. We have used this method in three step search (TSS) and four step search and compared the performance with already existing block matching algorithm.This thesis work proposes fast sub-pixel motion estimation techniques having lower computational complexity. The proposed methods are based on mathematical models of the motion compensated prediction errors in compressing moving pictures. Unlike conventional hierarchical motion estimation techniques, the proposed methods avoid sub-pixel interpolation and subsequent secondary search after the integer-precision motion estimation, resulting in reduced computational time. In order to decide the coefficients of the models, the motion-compensated prediction errors of the neighboring pixels around the integer-pixel motion vector are utilized

Traitement des signaux et images en temps réel ("implantation de H.264 sur MPSoC")

Cette thèse est élaborée en cotutelle entre l université Badji Mokhtar (Laboratoire LERICA) et l université de bourgogne (Laboratoire LE2I, UMR CNRS 5158). Elle constitue une contribution à l étude et l implantation de l encodeur H.264/AVC. Durent l évolution des normes de compression vidéo, une réalité sure est vérifiée de plus en plus : avoir une bonne performance du processus de compression nécessite l élaboration d équipements beaucoup plus performants en termes de puissance de calcul, de flexibilité et de portabilité et ceci afin de répondre aux exigences des différents traitements et satisfaire au critère Temps Réel . Pour assurer un temps réel pour ce genre d applications, une solution reste possible est l utilisation des systèmes sur puce (SoC) ou bien des systèmes multiprocesseurs sur puce (MPSoC) implantés sur des plateformes reconfigurables à base de circuit FPGA. L objective de cette thèse consiste à l étude et l implantation des algorithmes de traitement des signaux et images et en particulier la norme H.264/AVC, et cela dans le but d assurer un temps réel pour le cycle codage-décodage. Nous utilisons deux plateformes FPGA de Xilinx (ML501 et XUPV5). Dans la littérature, il existe déjà plusieurs implémentations du décodeur. Pour l encodeur, malgré les efforts énormes réalisés, il reste toujours du travail pour l optimisation des algorithmes et l extraction des parallélismes possibles surtout avec une variété de profils et de niveaux de la norme H.264/AVC.Dans un premier temps de cette thèse, nous proposons une implantation matérielle d un contrôleur mémoire spécialement pour l encodeur H.264/AVC. Ce contrôleur est réalisé en ajoutant, au contrôleur mémoire DDR2 des deux plateformes de Xilinx, une couche intelligente capable de calculer les adresses et récupérer les données nécessaires pour les différents modules de traitement de l encodeur. Ensuite, nous proposons des implantations matérielles (niveau RTL) des modules de traitement de l encodeur H.264. Sur ces implantations, nous allons exploiter les deux principes de parallélisme et de pipelining autorisé par l encodeur en vue de la grande dépendance inter-blocs. Nous avons ainsi proposé plusieurs améliorations et nouvelles techniques dans les modules de la chaine Intra et le filtre anti-blocs. A la fin de cette thèse, nous utilisons les modules réalisés en matériels pour la l implantation Matérielle/logicielle de l encodeur H.264/AVC. Des résultats de synthèse et de simulation, en utilisant les deux plateformes de Xilinx, sont montrés et comparés avec les autres implémentations existantesThis thesis has been carried out in joint supervision between the Badji Mokhtar University (LERICA Laboratory) and the University of Burgundy (LE2I laboratory, UMR CNRS 5158). It is a contribution to the study and implementation of the H.264/AVC encoder. The evolution in video coding standards have historically demanded stringent performances of the compression process, which imposes the development of platforms that perform much better in terms of computing power, flexibility and portability. Such demands are necessary to fulfill requirements of the different treatments and to meet "Real Time" processing constraints. In order to ensure real-time performances, a possible solution is to made use of systems on chip (SoC) or multiprocessor systems on chip (MPSoC) built on platforms based reconfigurable FPGAs. The objective of this thesis is the study and implementation of algorithms for signal and image processing (in particular the H.264/AVC standard); especial attention was given to provide real-time coding-decoding cycles. We use two FPGA platforms (ML501 and XUPV5 from Xilinx) to implement our architectures. In the literature, there are already several implementations of the decoder. For the encoder part, despite the enormous efforts made, work remains to optimize algorithms and extract the inherent parallelism of the architecture. This is especially true with a variety of profiles and levels of H.264/AVC. Initially, we proposed a hardware implementation of a memory controller specifically targeted to the H.264/AVC encoder. This controller is obtained by adding, to the DDR2 memory controller, an intelligent layer capable of calculating the addresses and to retrieve the necessary data for several of the processing modules of the encoder. Afterwards, we proposed hardware implementations (RTL) for the processing modules of the H.264 encoder. In these implementations, we made use of principles of parallelism and pipelining, taking into account the constraints imposed by the inter-block dependency in the encoder. We proposed several enhancements and new technologies in the channel Intra modules and the deblocking filter. At the end of this thesis, we use the modules implemented in hardware for implementing the H.264/AVC encoder in a hardware/software design. Synthesis and simulation results, using both platforms for Xilinx, are shown and compared with other existing implementationsDIJON-BU Doc.électronique (212319901) / SudocSudocFranceF

Implementing video compression algorithms on reconfigurable devices

The increasing density offered by Field Programmable Gate Arrays(FPGA), coupled with their short design cycle, has made them a popular choice for implementing a wide range of algorithms and complete systems. In this thesis the implementation of video compression algorithms on FPGAs is studied. Two areas are specifically focused on; the integration of a video encoder into a complete system and the power consumption of FPGA based video encoders. Two FPGA based video compression systems are described, one which targets surveillance applications and one which targets video conferencing applications. The FPGA video surveillance system makes use of a novel memory format to improve the efficiency with which input video sequences can be loaded over the system bus. The power consumption of a FPGA video encoder is analyzed. The results indicating that the motion estimation encoder stage requires the most power consumption. An algorithm, which reuses the intra prediction results generated during the encoding process, is then proposed to reduce the power consumed on an FPGA video encoder’s external memory bus. Finally, the power reduction algorithm is implemented within an FPGA video encoder. Results are given showing that, in addition to reducing power on the external memory bus, the algorithm also reduces power in the motion estimation stage of a FPGA based video encoder

Codificação de vídeo: priorização do menor custo de codificação na otimização em taxa-distorção

Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2009.O presente trabalho propõe duas novas estratégias para compressão de sinais de vídeo através de algoritmos otimizados em taxa-distorção (RD), focando aplicações típicas de vídeo digital para operação em baixas taxas de bits. As estratégias propostas são implementadas em um codificador de vídeo baseado no padrão H.264, o qual apresenta uma alta complexidade computacional devido principalmente ao grande número de modos de codificação disponível. São apresentadas duas propostas de redução da complexidade, mantendo o desempenho RD próximo àquele do codificador H.264 otimizado em RD usando busca exaustiva. A primeira proposta (denominada rate sorting and truncation - RST) realiza o ordenamento tanto dos vetores de movimento (VMs) quanto dos modos de codificação em ordem ascendente de taxa de bits. O processo de codificação é interrompido quando a taxa de bits dos novos VMs e modos de codificação exceder à menor taxa já obtida para um pré-estabelecido nível de qualidade de imagem. Assim, um grande número de VMs e diversos modos de codificação são descartados antes que sejam avaliados. A segunda proposta consiste em um algoritmo rápido, baseado no perfil de distribuição de vetores do codificador H.264, para estimação de movimento (denominado logarithmic diamond shape search - LDSS). O uso da estratégia RST associada ao algoritmo LDSS reduz até 98% a carga computacional com perda marginal de desempenho RD.This research work proposes two new video compression strategies, aiming at typical low bit rate video applications using rate-distortion (RD) optimized algorithms. The proposed strategies are implemented on an H.264 video encoder, which has high computational complexity due mainly to the large number of coding modes available. Two approaches are presented for reducing the encoder computational complexity, maintaining the RD performance close to the full search RD optimized H.264 encoder. The first approach (termed rate sorting and truncation - RST) is based on sorting the motion vectors (MVs) and coding modes in an ascending rate order. This sorting and encoding process, which is stopped when the rate value exceeds the previous best rate for a required image quality level, allows the elimination of MVs and coding modes before checking their distortion. Apart from obtaining a significant complexity reduction, the process still remains optimized in RD sense. The second approach is an algorithm (termed logarithmic diamond shape search - LDSS), which explores the MVs distribution profile for the RD optimized H.264 encoder. The use of the RST strategy associated with LDSS algorithm yields up to a 98% reduction in the computational burden, with insignificant RD performance loss