21,736 research outputs found
A second-order class-D audio amplifier
Class-D audio amplifiers are particularly efficient, and this efficiency has led to their ubiquity in a wide range of modern electronic appliances. Their output takes the form of a high-frequency square wave whose duty cycle (ratio of on-time to off-time) is modulated at low frequency according to the audio signal. A mathematical model is developed here for a second-order class-D amplifier design (i.e., containing one second-order integrator) with negative feedback. We derive exact expressions for the dominant distortion terms, corresponding to a general audio input signal, and confirm these predictions with simulations. We also show how the observed phenomenon of “pulse skipping” arises from an instability of the analytical solution upon which the distortion calculations are based, and we provide predictions of the circumstances under which pulse skipping will take place, based on a stability analysis. These predictions are confirmed by simulations
autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate Components
Approximate computing is an emerging paradigm for developing highly
energy-efficient computing systems such as various accelerators. In the
literature, many libraries of elementary approximate circuits have already been
proposed to simplify the design process of approximate accelerators. Because
these libraries contain from tens to thousands of approximate implementations
for a single arithmetic operation it is intractable to find an optimal
combination of approximate circuits in the library even for an application
consisting of a few operations. An open problem is "how to effectively combine
circuits from these libraries to construct complex approximate accelerators".
This paper proposes a novel methodology for searching, selecting and combining
the most suitable approximate circuits from a set of available libraries to
generate an approximate accelerator for a given application. To enable fast
design space generation and exploration, the methodology utilizes machine
learning techniques to create computational models estimating the overall
quality of processing and hardware cost without performing full synthesis at
the accelerator level. Using the methodology, we construct hundreds of
approximate accelerators (for a Sobel edge detector) showing different but
relevant tradeoffs between the quality of processing and hardware cost and
identify a corresponding Pareto-frontier. Furthermore, when searching for
approximate implementations of a generic Gaussian filter consisting of 17
arithmetic operations, the proposed approach allows us to identify
approximately highly important implementations from possible
solutions in a few hours, while the exhaustive search would take four months on
a high-end processor.Comment: Accepted for publication at the Design Automation Conference 2019
(DAC'19), Las Vegas, Nevada, US
Electronic and photonic switching in the atm era
Broadband networks require high-capacity switches in order to properly manage large amounts of traffic fluxes. Electronic and photonic technologies are being used to achieve this objective both allowing different multiplexing and switching techniques. Focusing on the asynchronous transfer mode (ATM), the inherent different characteristics of electronics and photonics makes different architectures feasible. In this paper, different switching structures are described, several ATM switching architectures which have been recently implemented are presented and the implementation characteristics discussed. Three diverse points of view are given from the electronic research, the photonic research and the commercial switches. Although all the architectures where successfully tested, they should also follow different market requirements in order to be commercialised. The characteristics are presented and the architectures projected over them to evaluate their commercial capabilities.Peer ReviewedPostprint (published version
A Study of Optimal 4-bit Reversible Toffoli Circuits and Their Synthesis
Optimal synthesis of reversible functions is a non-trivial problem. One of
the major limiting factors in computing such circuits is the sheer number of
reversible functions. Even restricting synthesis to 4-bit reversible functions
results in a huge search space (16! {\approx} 2^{44} functions). The output of
such a search alone, counting only the space required to list Toffoli gates for
every function, would require over 100 terabytes of storage. In this paper, we
present two algorithms: one, that synthesizes an optimal circuit for any 4-bit
reversible specification, and another that synthesizes all optimal
implementations. We employ several techniques to make the problem tractable. We
report results from several experiments, including synthesis of all optimal
4-bit permutations, synthesis of random 4-bit permutations, optimal synthesis
of all 4-bit linear reversible circuits, synthesis of existing benchmark
functions; we compose a list of the hardest permutations to synthesize, and
show distribution of optimal circuits. We further illustrate that our proposed
approach may be extended to accommodate physical constraints via reporting
LNN-optimal reversible circuits. Our results have important implications in the
design and optimization of reversible and quantum circuits, testing circuit
synthesis heuristics, and performing experiments in the area of quantum
information processing.Comment: arXiv admin note: substantial text overlap with arXiv:1003.191
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