Full observation of single-atom dynamics in cavity QED

We report the use of broadband heterodyne spectroscopy to perform continuous measurement of the interaction energy between one atom and a high-finesse optical cavity, during individual transit events of $\sim 250$ $\mu$s duration. Measurements over a wide range of atom-cavity detunings reveal the transition from resonant to dispersive coupling, via the transfer of atom-induced signals from the amplitude to the phase of light transmitted through the cavity. By suppressing all sources of excess technical noise, we approach a measurement regime in which the broadband photocurrent may be interpreted as a classical record of conditional quantum evolution in the sense of recently developed quantum trajectory theories.Comment: Submitted to Applied Physics B. Uses Revtex, 13 pages with 11 EPS figure

Fast synchronization 3R burst-mode receivers for passive optical networks

This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed

Digital Centric Multi-Gigabit SerDes Design and Verification

Advances in semiconductor manufacturing still lead to ever decreasing feature sizes and constantly allow higher degrees of integration in application specific integrated circuits (ASICs). Therefore the bandwidth requirements on the external interfaces of such systems on chips (SoC) are steadily growing. Yet, as the number of pins on these ASICs is not increasing in the same pace - known as pin limitation - the bandwidth per pin has to be increased. SerDes (Serializer/Deserializer) technology, which allows to transfer data serially at very high data rates of 25Gbps and more is a key technology to overcome pin limitation and exploit the computing power that can be achieved in todays SoCs. As such SerDes blocks together with the digital logic interfacing them form complex mixed signal systems, verification of performance and functional correctness is very challenging. In this thesis a novel mixed-signal design methodology is proposed, which tightly couples model and implementation in order to ensure consistency throughout the design cycles and hereby accelerate the overall implementation flow. A tool flow that has been developed is presented, which integrates well into state of the art electronic design automation (EDA) environments and enables the usage of this methodology in practice. Further, the design space of todays high-speed serial links is analyzed and an architecture is proposed, which pushes complexity into the digital domain in order to achieve robustness, portability between manufacturing processes and scaling with advanced node technologies. The all digital phase locked loop (PLL) and clock data recovery (CDR), which have been developed are described in detail. The developed design flow was used for the implementation of the SerDes architecture in a 28nm silicon process and proved to be indispensable for future projects

The G0 Experiment: Apparatus for Parity-Violating Electron Scattering Measurements at Forward and Backward Angles

In the G0 experiment, performed at Jefferson Lab, the parity-violating elastic scattering of electrons from protons and quasi-elastic scattering from deuterons is measured in order to determine the neutral weak currents of the nucleon. Asymmetries as small as 1 part per million in the scattering of a polarized electron beam are determined using a dedicated apparatus. It consists of specialized beam-monitoring and control systems, a cryogenic hydrogen (or deuterium) target, and a superconducting, toroidal magnetic spectrometer equipped with plastic scintillation and aerogel Cerenkov detectors, as well as fast readout electronics for the measurement of individual events. The overall design and performance of this experimental system is discussed.Comment: Submitted to Nuclear Instruments and Method

The Telecommunications and Data Acquisition Report

This publication, one of a series formerly titled The Deep Space Network Progress Report, documents DSN progress in flight project support, tracking and data acquisition research and technology, network engineering, hardware and software implementation, and operations. In addition, developments in Earth-based radio technology as applied to geodynamics, astrophysics and the radio search for extraterrestrial intelligence are reported

Design and Implementation of Internal Model Based Controllers for DC/ AC Power Converters

The aim of this thesis is to design and implement an advanced control system for a working three-phase DC to AC power converter. Compared to' the traditional PI controller used widely in industry, the new voltage controller can track the reference voltage with improved accuracy and efficiency in the presence of different kind of local loads, and also works well in the single phase voltage control. This voltage controller is combined with a power controller to yield a complete controller. An important aspect of this work is the hardware implementation of the whole system. Main parts ofthis thesis are: ???????? 1. Review ofH-infinity and repetitive control techniques and their applications in power converters. 2. Design of a new voltage controller to eliminate the DC component in the output voltages, and taking into account the practical issues such as the processing delay due to the digital signal processor (DSP) implementation. 3. Modelling and simulation of the converter system incorporating different control techniques and with different kinds of loads. 4. Hardware implementation and the two-processor controller. The parallel communication between the DSPs. 5. The main problems encountered in???????????????????? hardware implementation and programming. The software used to initialize DSPs, implement the discretetime voltage controller and other functions such ~ generations of space vector pulse width modulation (SVPWM) signals, circuit protections, analog to digital (AD) cOl)versions, data transmission, etc. 6. Experimental results the under circumstances of no load connected to the converter, pure three-phase resistive loads, three-phase unbalanced resistive' loads and the series resistor-inductor loads. /Imperial Users onl

Clock Generator Circuits for Low-Power Heterogeneous Multiprocessor Systems-on-Chip

In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core. For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed. The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed. The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications. Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies.In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können. Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren. Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien

LISA Metrology System - Final Report

Gravitational Waves will open an entirely new window to the Universe, different from all other astronomy in that the gravitational waves will tell us about large-scale mass motions even in regions and at distances totally obscured to electromagnetic radiation. The most interesting sources are at low frequencies (mHz to Hz) inaccessible on ground due to seismic and other unavoidable disturbances. For these sources observation from space is the only option, and has been studied in detail for more than 20 years as the LISA concept. Consequently, The Gravitational Universe has been chosen as science theme for the L3 mission in ESA's Cosmic Vision program. The primary measurement in LISA and derived concepts is the observation of tiny (picometer) pathlength fluctuations between remote spacecraft using heterodyne laser interferometry. The interference of two laser beams, with MHz frequency difference, produces a MHz beat note that is converted to a photocurrent by a photodiode on the optical bench. The gravitational wave signal is encoded in the phase of this beat note. The next, and crucial, step is therefore to measure that phase with µcycle resolution in the presence of noise and other signals. This measurement is the purpose of the LISA metrology system and the subject of this report

Ku-band system design study and TDRSS interface analysis

The capabilities of the Shuttle/TDRSS link simulation program (LinCsim) were expanded to account for radio frequency interference (RFI) effects on the Shuttle S-band links, the channel models were updated to reflect the RFI related hardware changes, the ESTL hardware modeling of the TDRS communication payload was reviewed and evaluated, in LinCsim the Shuttle/TDRSS signal acquisition was modeled, LinCsim was upgraded, and possible Shuttle on-orbit navigation techniques was evaluated