Designing Change Assimilation Process using Close-up Down Graph for Switch Based Networks

In today’s modern switch-based interconnected systems require high performance, reliability and availability. These switch based networks changes their topologies due to hot expansion of components, link or node activation and deactivation. Device failures in high-speed computer networks can also result in topological changes. Also, component failures, addition and deletion of components cause changes in the topology and routing paths supplied by the interconnection network. Therefore a network reconfiguration algorithm must be executed to reestablish the connectivity between the network nodes. Now we have two types of reconfiguration techniques and they are static reconfiguration and dynamic reconfiguration. Static reconfiguration techniques significantly reduce network service since the application traffic is temporally stopped in order to avoid deadlocks. But unfortunately this has negative impact on network service availability. Dynamic network reconfiguration is the process of changing from one routing function to another routing function while the network remains up and running. While performing dynamic network reconfiguration, the main challenge is to avoid deadlocks and provide network service availability along with reduced packet dropping rate. In this paper we demonstrate how dynamic reconfiguration is more efficient than the static reconfiguration for switch based networks

UP-DOWN ROUTING BASED DEADLOCK FREE DYNAMIC RECONFIGURATION IN HIGH SPEED LOCAL AREA NETWORKS

Dynamic reconfiguration of high speed switched network is the process of changing from one routing function to another while the network remains in running mode Current distributed switch-based interconnected systems require high performance reliability and availability These systems changes their topologies due to hot expansion of components link or node activation and deactivation Therefore in order to support hard real-time and distributed multimedia applications over a high speed network we need to avoid discarding packets when the topology changes Thus a dynamic reconfiguration algorithm updates the routing tables of these interconnected switches according to new changed topology without stopping the traffic Here we propose an improved deadlock-free partial progressive reconfiguration PPR technique based on UP DOWN routing algorithm that assigns the directions to various links of high-speed switched networks based on pre-order traversal of computed spanning tree This improved technique gives better performance as compared to traditional PPR by minimizing the path length of packets to be transmitted Moreover the proposed reconfiguration strategy makes the optimize use of all operational links and reduces the traffic congestion in the network The simulated results are compared with traditional PP

Application-Aware Deadlock-Free Oblivious Routing

Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framework for application-aware routing that assures deadlock-freedom under one or more channels by forcing routes to conform to an acyclic channel dependence graph. Arbitrary minimal routes can be made deadlock-free through appropriate static channel allocation when two or more channels are available. Given bandwidth estimates for flows, we present a mixed integer-linear programming (MILP) approach and a heuristic approach for producing deadlock-free routes that minimize maximum channel load. The heuristic algorithm is calibrated using the MILP algorithm and evaluated on a number of benchmarks through detailed network simulation. Our framework can be used to produce application-aware routes that target the minimization of latency, number of flows through a link, bandwidth, or any combination thereof

Application-Aware Deadlock-Free Oblivious Routing

Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framework for application-aware routing that assures deadlock-freedom under one or more channels by forcing routes to conform to an acyclic channel dependence graph. Arbitrary minimal routes can be made deadlock-free through appropriate static channel allocation when two or more channels are available. Given bandwidth estimates for flows, we present a mixed integer-linear programming (MILP) approach and a heuristic approach for producing deadlock-free routes that minimize maximum channel load. The heuristic algorithm is calibrated using the MILP algorithm and evaluated on a number of benchmarks through detailed network simulation. Our framework can be used to produce application-aware routes that target the minimization of latency, number of flows through a link, bandwidth, or any combination thereof

Bandwidth-sensitive oblivious routing

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Includes bibliographical references (p. 81-83).Traditional oblivious routing algorithms either do not take into account the bandwidth demand, or assume that each flow has its own private channel to guarantee deadlock freedom. Though adaptive routing schemes can react to varying network traffic, they require complicated router designs. In this thesis, we present a polynomial-time heuristic routing algorithm that takes bandwidth requirements of each flow into account to minimize maximum channel load. The heuristic algorithm has two variants. The first one produces a deadlock-free route. The second one produces a minimal route, and is deadlock-free with two or more virtual channels assuming proper VC allocation. Both routing algorithms are oblivious, and need only simple router designs. The performance of each bandwidth-sensitive routing algorithm is evaluated against dimension-order routing and against the other on a number of benchmarks.by Tina Wen.M.Eng

Efficient mechanisms to provide fault tolerance in interconnection networks for pc clusters

Actualmente, los clusters de PC son un alternativa rentable a los computadores paralelos. En estos sistemas, miles de componentes (procesadores y/o discos duros) se conectan a través de redes de interconexión de altas prestaciones. Entre las tecnologías de red actualmente disponibles para construir clusters, InfiniBand (IBA) ha emergido como un nuevo estándar de interconexión para clusters. De hecho, ha sido adoptado por muchos de los sistemas más potentes construidos actualmente (lista top500). A medida que el número de nodos aumenta en estos sistemas, la red de interconexión también crece. Junto con el aumento del número de componentes la probabilidad de averías aumenta dramáticamente, y así, la tolerancia a fallos en el sistema en general, y de la red de interconexión en particular, se convierte en una necesidad. Desafortunadamente, la mayor parte de las estrategias de encaminamiento tolerantes a fallos propuestas para los computadores masivamente paralelos no pueden ser aplicadas porque el encaminamiento y las transiciones de canal virtual son deterministas en IBA, lo que impide que los paquetes eviten los fallos. Por lo tanto, son necesarias nuevas estrategias para tolerar fallos. Por ello, esta tesis se centra en proporcionar los niveles adecuados de tolerancia a fallos a los clusters de PC, y en particular a las redes IBA. En esta tesis proponemos y evaluamos varios mecanismos adecuados para las redes de interconexión para clusters. El primer mecanismo para proporcionar tolerancia a fallos en IBA (al que nos referimos como encaminamiento tolerante a fallos basado en transiciones; TFTR) consiste en usar varias rutas disjuntas entre cada par de nodos origen-destino y seleccionar la ruta apropiada en el nodo fuente usando el mecanismo APM proporcionado por IBA. Consiste en migrar las rutas afectadas por el fallo a las rutas alternativas sin fallos. Sin embargo, con este fin, es necesario un algoritmo eficiente de encaminamiento capaz de proporcionar suficientesMontañana Aliaga, JM. (2008). Efficient mechanisms to provide fault tolerance in interconnection networks for pc clusters [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/2603Palanci

Diseño de mecanismos eficientes para la gestión de subredes infiniband

El objetivo principal de esta tesis doctoral es contribuir al desarrollo de mecanismos de asimilación de cambios toplogicos para la arquitectura de red infiniband. En una primera fase, se ha diseñado y evaluado un primer prototipo de mecanismo de gestión. Su evaluación nos ha permitido identificar los principales cuellos de botella en el proceso de adaptación al cambio. A continuación, se han propuesto mecanismos optimizados para cada una de las tareas involucradas en dicho proceso: la detección del cambio topológico, la adquisición de la nueva topología de la red, el cómputo de nuevas rutas y la distribución de tables de encaminamiento actualizadas a los conmutadores de la red. El resultado es un mecanismo de gestión totalmente compatible con la especificación de infiniband, fácilmente implementable en sistemas comerciales, y casi transparente desde el punto de vista de las aplicaciones a las que da servicio la red