Modelling of interconnects in 3DIC based on layered green functions

As traditional CMOS scaling pace gradually slows down, three-dimensional (3D) integration offers another dimension of in the ”More-than-Moore” era. In this dissertation, a number of investigations were conducted to better model interconnects in 3D integrated circuit (IC), to evaluate electrical behavior including delay, power consumption, signal integrity (SI), and power integrity (PI) for 3D ICs. Partial Element Equivalent Circuit (PEEC) method with layered Green’s function is studied here, since it consumes less computational resources and provides better physical insight to model the interconnects in 3DIC for high-speed digital circuits. The work is organized as a series of papers. The first paper reviewed the fundamental methods to derive layered Green’s function in spectral domain using discrete complex image method (DCIM) and analyzed the effects of each Green function terms to model silicon interconnects. The second paper proposed a unique method to extract poles near branch cut in complex kp plane, to accurately extract surface wave effects. The last paper proposed a new equivalent circuit model for coplanar waveguide (CPW) structure on 3DIC. The silicon effects on series inductance were also studied by employing the modified Green functions with semiconductor images at a complex distance from spectral-domain analysis. --Abstract, page iii

Eigenmode-based capacitance calculations with applications in passivation layer design

The design of high-speed metallic interconnects such as microstrips requires the correct characterization of both the conductors and the surrounding dielectric environment, in order to accurately predict their propagation characteristics. A fast boundary integral equation approach is obtained by modeling all materials as equivalent surface charge densities in free space. The capacitive behavior of a finite dielectric environment can then be determined by means of a transformation matrix, relating these charge densities to the boundary value of the electric potential. In this paper, a new calculation method is presented for the important case that the dielectric environment is composed of homogeneous rectangles. The method, based on a surface charge expansion in terms of the Robin eigenfunctions of the considered rectangles, is not only more efficient than traditional methods, but is also more accurate, as shown in some numerical experiments. As an application, the design and behavior of a microstrip passivation layer is treated in some detail

Peec-Based On-Chip Pdn Impedance Modeling using Layered Green\u27s Function

This paper presents an impedance model of on-chip power distribution network (PDN), which is an efficient criterion for estimating simultaneous switching noises (SSNs) on 3-D integrated circuit (IC). The impedance of on-chip PDN, including the effect of silicon substrate, is accurately modeled based on partial element equivalent circuit (PEEC) and layered Green\u27s function (LGF). The equivalent circuit model of PDN is extracted based on the physical dimensions and electrical material characteristic of PDN at first. And then the LGF is used to consider the effect of silicon substrate for improving the accuracy of on-chip PDN impedance model. The effectiveness of proposed model has been validated by full wave simulation. The high order resonance of PDN impedance can also be accurately predicted

Cmos Rotary Traveling Wave Oscillators (Rtwos)

Rotary Traveling Wave Oscillator (RTWO) represents a transmission line based technology for multi-gigahertz multiple phase clock generation. RTWO is known for providing low jitter and low phase noise signals but the issue of high power consumption is a major drawback in its application. Direction of wave propagation is random and is determined by the least resistance path in the absence of an external direction control circuit. The objective of this research is to address some of the problems of RTWO design, including high power consumption, uncertainty of propagation direction and optimization of design variables. Included is the modeling of RTWO for sensitivity, phase noise and power analysis. Research objectives were met through design, simulation and implementation. Different designs of RTWO in terms of ring size and number of amplifier stages were implemented and tested. Design tools employed include Agilent ADS, Cadence EDA, SONNET and Altium PCB Designer. Test chip was fabricated using IBM 0.18 μm RF CMOS technology. Performance measures of interest are tuning range, phase noise and power consumption. Agilent ADS and SONNET were used for electromagnetic modeling of transmission lines and electromagnetic field radiation. For each design, electromagnetic simulations were carried out followed by oscillation synthesis based on circuit simulation in Cadence Spectre. RTWO frequencies between 2 GHz and 12 GHz were measured based on the ring size of transmission lines. Simulated microstrip transmission line segments had a quality factor between 5.5 and 18. For the various designs, power consumption ranged from 20 mW to 120 mW. Measured phase noise ranged between -123 dBc/Hz and -87 dBc/Hz at 1 MHz offset. Development also included the design of a wide band buffer and a printed circuit board with high signal integrity for accurate measurement of oscillation frequency and other performance measures. Simulated performance, schematics and measurement results are presented