Single-Event Upset Analysis and Protection in High Speed Circuits

The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a single event upset (SEU) caused by particle strike on the internal nodes of a flip-flo

Plug & Test at System Level via Testable TLM Primitives

With the evolution of Electronic System Level (ESL) design methodologies, we are experiencing an extensive use of Transaction-Level Modeling (TLM). TLM is a high-level approach to modeling digital systems where details of the communication among modules are separated from the those of the implementation of functional units. This paper represents a first step toward the automatic insertion of testing capabilities at the transaction level by definition of testable TLM primitives. The use of testable TLM primitives should help designers to easily get testable transaction level descriptions implementing what we call a "Plug & Test" design methodology. The proposed approach is intended to work both with hardware and software implementations. In particular, in this paper we will focus on the design of a testable FIFO communication channel to show how designers are given the freedom of trading-off complexity, testability levels, and cos

Earth Radiation Budget Experiment (ERBE) scanner instrument anomaly investigation

The results of an ad-hoc committee investigation of in-Earth orbit operational anomalies noted on two identical Earth Radiation Budget Experiment (ERBE) Scanner instruments on two different spacecraft busses is presented. The anomalies are attributed to the bearings and the lubrication scheme for the bearings. A detailed discussion of the pertinent instrument operations, the approach of the investigation team and the current status of the instruments now in Earth orbit is included. The team considered operational changes for these instruments, rework possibilities for the one instrument which is waiting to be launched, and preferable lubrication considerations for specific space operational requirements similar to those for the ERBE scanner bearings

Space programs summary no. 37-63, volume 1 for the period 1 March - 30 April 1970. Flight projects

Mariner Mars 1971, Mariner Venus-Mercury 1973 and Viking Orbiter 1975 status report

Discrete input equipment design study

The study to improve the reliability of the LUT system by discrete input equipment (DIE) is reported. Subjects discussed include: specifications, packaging, aircraft integrated systems, and word formats DIE. It is recommended that maximal use of advanced technology be made, particularly the "know how' developed on the Saturn project

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Streak camera receiver definition study

Detailed streak camera definition studies were made as a first step toward full flight qualification of a dual channel picosecond resolution streak camera receiver for the Geoscience Laser Altimeter and Ranging System (GLRS). The streak camera receiver requirements are discussed as they pertain specifically to the GLRS system, and estimates of the characteristics of the streak camera are given, based upon existing and near-term technological capabilities. Important problem areas are highlighted, and possible corresponding solutions are discussed