Cellular Automata with Synthetic Image A Secure Image Communication with Transform Domain

    Image encryption has attained a great attention due to the necessity to safeguard confidential images. Digital documents, site images, battlefield photographs, etc. need a secure approach for sharing in an open channel. Hardware – software co-design is a better option for exploiting unique features to cipher the confidential images. Cellular automata (CA) and synthetic image influenced transform domain approach for image encryption is proposed in this paper. The digital image is initially divided into four subsections by applying integer wavelet transform. Confusion is accomplished on low – low section of the transformed image using CA rules 90 and 150. The first level of diffusion with consecutive XORing operation of image pixels is initiated by CA rule 42. A synthetic random key image is developed by extracting true random bits generated by Cyclone V field programmable gate array 5CSEMA5F31C6. This random image plays an important role in second level of diffusion. The proposed confusion and two level diffusion assisted image encryption approach has been validated through the entropy, correlation, histogram, number of pixels change rate, unified average change intensity, contrast and encryption quality analyses

Cellular Automata and Randomization: A Structural Overview

The chapter overviews the methods, algorithms, and architectures for random number generators based on cellular automata, as presented in the scientific literature. The variations in linear and two-dimensional cellular automata model and their features are discussed in relation to their applications as randomizers. Additional memory layers, functional nonuniformity in space or time, and global feedback are examples of such variations. Successful applications of cellular automata random number/signal generators (both software and hardware) reported in the scientific literature are also reviewed. The chapter includes an introductory presentation of the mathematical (ideal) model of cellular automata and its implementation as a computing model, emphasizing some important theoretical debates regarding the complexity and universality of cellular automata

Recent Advancements on Symmetric Cryptography Techniques -A Comprehensive Case Study

Now a day2019;s Cryptography is one of the broad areas for researchers; because of the conventional block cipher has lost its potency due to the sophistication of modern systems that can break it by brute force. Due to its importance, several cryptography techniques and algorithms are adopted by many authors to secure the data, but still there is a scope to improve the previous approaches. For this necessity, we provide the comprehensive survey which will help the researchers to provide better techniques

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs

Dynamically reconfigurable bio-inspired hardware

During the last several years, reconfigurable computing devices have experienced an impressive development in their resource availability, speed, and configurability. Currently, commercial FPGAs offer the possibility of self-reconfiguring by partially modifying their configuration bitstream, providing high architectural flexibility, while guaranteeing high performance. These configurability features have received special interest from computer architects: one can find several reconfigurable coprocessor architectures for cryptographic algorithms, image processing, automotive applications, and different general purpose functions. On the other hand we have bio-inspired hardware, a large research field taking inspiration from living beings in order to design hardware systems, which includes diverse topics: evolvable hardware, neural hardware, cellular automata, and fuzzy hardware, among others. Living beings are well known for their high adaptability to environmental changes, featuring very flexible adaptations at several levels. Bio-inspired hardware systems require such flexibility to be provided by the hardware platform on which the system is implemented. In general, bio-inspired hardware has been implemented on both custom and commercial hardware platforms. These custom platforms are specifically designed for supporting bio-inspired hardware systems, typically featuring special cellular architectures and enhanced reconfigurability capabilities; an example is their partial and dynamic reconfigurability. These aspects are very well appreciated for providing the performance and the high architectural flexibility required by bio-inspired systems. However, the availability and the very high costs of such custom devices make them only accessible to a very few research groups. Even though some commercial FPGAs provide enhanced reconfigurability features such as partial and dynamic reconfiguration, their utilization is still in its early stages and they are not well supported by FPGA vendors, thus making their use difficult to include in existing bio-inspired systems. In this thesis, I present a set of architectures, techniques, and methodologies for benefiting from the configurability advantages of current commercial FPGAs in the design of bio-inspired hardware systems. Among the presented architectures there are neural networks, spiking neuron models, fuzzy systems, cellular automata and random boolean networks. For these architectures, I propose several adaptation techniques for parametric and topological adaptation, such as hebbian learning, evolutionary and co-evolutionary algorithms, and particle swarm optimization. Finally, as case study I consider the implementation of bio-inspired hardware systems in two platforms: YaMoR (Yet another Modular Robot) and ROPES (Reconfigurable Object for Pervasive Systems); the development of both platforms having been co-supervised in the framework of this thesis

Integrating Non-linear and Linear Diffusion Techniques to Prevent Fault Attacks in Advanced Encryption Standard to Enhance Security of 4G-LTE Networks

Long term evolution based fourth generation (4G) mobile technology has provided a platform for fast and efficient wireless communication. The advanced encryption standard (AES) is one of the three cryptographic algorithms used in 4G networks for encryption of sensitive data. In spite of offering high immunity, AES is still vulnerable to few attacks. This weakness in AES algorithm makes 4G susceptible to several security issues. This paper specifically focuses on fault attacks performed on AES. A fault induced in any one of the rounds of AES helps the attacker to derive information about the secret key. In this manner, these fault attacks pose a serious threat to wireless mobile communication as he or she may gain access to any network that is encrypted with AES. In earlier works, various countermeasures have been suggested to prevent them. However, each of these preventive measures has their own limitations and vulnerabilities. This paper proposes an enhanced method of preventing fault attacks in AES by incorporating a combination of non-linear and linear diffusion techniques. This method identifies if a fault has been injected and diffuses the fault well into the matrix, providing no information about the secret key to the attacker. The performance evaluation proves that the proposed prevention method outperforms the others in terms of time, cost and efficiency

Cryptographic primitives on reconfigurable platforms.

Tsoi Kuen Hung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 84-92).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Objectives --- p.3Chapter 1.3 --- Contributions --- p.3Chapter 1.4 --- Thesis Organization --- p.4Chapter 2 --- Background and Review --- p.6Chapter 2.1 --- Introduction --- p.6Chapter 2.2 --- Cryptographic Algorithms --- p.6Chapter 2.3 --- Cryptographic Applications --- p.10Chapter 2.4 --- Modern Reconfigurable Platforms --- p.11Chapter 2.5 --- Review of Related Work --- p.14Chapter 2.5.1 --- Montgomery Multiplier --- p.14Chapter 2.5.2 --- IDEA Cipher --- p.16Chapter 2.5.3 --- RC4 Key Search --- p.17Chapter 2.5.4 --- Secure Random Number Generator --- p.18Chapter 2.6 --- Summary --- p.19Chapter 3 --- The IDEA Cipher --- p.20Chapter 3.1 --- Introduction --- p.20Chapter 3.2 --- The IDEA Algorithm --- p.21Chapter 3.2.1 --- Cipher Data Path --- p.21Chapter 3.2.2 --- S-Box: Multiplication Modulo 216 + 1 --- p.23Chapter 3.2.3 --- Key Schedule --- p.24Chapter 3.3 --- FPGA-based IDEA Implementation --- p.24Chapter 3.3.1 --- Multiplication Modulo 216 + 1 --- p.24Chapter 3.3.2 --- Deeply Pipelined IDEA Core --- p.26Chapter 3.3.3 --- Area Saving Modification --- p.28Chapter 3.3.4 --- Key Block in Memory --- p.28Chapter 3.3.5 --- Pipelined Key Block --- p.30Chapter 3.3.6 --- Interface --- p.31Chapter 3.3.7 --- Pipelined Design in CBC Mode --- p.31Chapter 3.4 --- Summary --- p.32Chapter 4 --- Variable Radix Montgomery Multiplier --- p.33Chapter 4.1 --- Introduction --- p.33Chapter 4.2 --- RSA Algorithm --- p.34Chapter 4.3 --- Montgomery Algorithm - Ax B mod N --- p.35Chapter 4.4 --- Systolic Array Structure --- p.36Chapter 4.5 --- Radix-2k Core --- p.37Chapter 4.5.1 --- The Original Kornerup Method (Bit-Serial) --- p.37Chapter 4.5.2 --- The Radix-2k Method --- p.38Chapter 4.5.3 --- Time-Space Relationship of Systolic Cells --- p.38Chapter 4.5.4 --- Design Correctness --- p.40Chapter 4.6 --- Implementation Details --- p.40Chapter 4.7 --- Summary --- p.41Chapter 5 --- Parallel RC4 Engine --- p.42Chapter 5.1 --- Introduction --- p.42Chapter 5.2 --- Algorithms --- p.44Chapter 5.2.1 --- RC4 --- p.44Chapter 5.2.2 --- Key Search --- p.46Chapter 5.3 --- System Architecture --- p.47Chapter 5.3.1 --- RC4 Cell Design --- p.47Chapter 5.3.2 --- Key Search --- p.49Chapter 5.3.3 --- Interface --- p.50Chapter 5.4 --- Implementation --- p.50Chapter 5.4.1 --- RC4 cell --- p.51Chapter 5.4.2 --- Floorplan --- p.53Chapter 5.5 --- Summary --- p.53Chapter 6 --- Blum Blum Shub Random Number Generator --- p.55Chapter 6.1 --- Introduction --- p.55Chapter 6.2 --- RRNG Algorithm . . --- p.56Chapter 6.3 --- PRNG Algorithm --- p.58Chapter 6.4 --- Architectural Overview --- p.59Chapter 6.5 --- Implementation --- p.59Chapter 6.5.1 --- Hardware RRNG --- p.60Chapter 6.5.2 --- BBS PRNG --- p.61Chapter 6.5.3 --- Interface --- p.66Chapter 6.6 --- Summary --- p.66Chapter 7 --- Experimental Results --- p.68Chapter 7.1 --- Design Platform --- p.68Chapter 7.2 --- IDEA Cipher --- p.69Chapter 7.2.1 --- Size of IDEA Cipher --- p.70Chapter 7.2.2 --- Performance of IDEA Cipher --- p.70Chapter 7.3 --- Variable Radix Systolic Array --- p.71Chapter 7.4 --- Parallel RC4 Engine --- p.75Chapter 7.5 --- BBS Random Number Generator --- p.76Chapter 7.5.1 --- Size --- p.76Chapter 7.5.2 --- Speed --- p.76Chapter 7.5.3 --- External Clock --- p.77Chapter 7.5.4 --- Random Performance --- p.78Chapter 7.6 --- Summary --- p.78Chapter 8 --- Conclusion --- p.81Chapter 8.1 --- Future Development --- p.83Bibliography --- p.8

Implementation of AES with Time Complexity Measurement for Various Input

Network Security has a major role in the development of data communication system, where more randomization in the secret keys increases the security as well as the complexity of the cryptography algorithms. In the recent years network security has become an important issue. Cryptography has come up as a solution which plays a vital role in the information security system against various attacks. This security mechanism uses the AES algorithm to scramble data into unreadable text which can only be decrypted with the associated key. The AES algorithm is limited only for text as an input. It also has, the more time complexity. So it suffers from vulnerabilities associated with another type of input and time constraints. So its challenge to implement the AES algorithm for various types of input and require less decryption time. The propose work demonstrate implementation of a 128-bit Advanced Encryption Standard (AES), which consists of both symmetric key encryption and decryption algorithms for input as a text, image and audio. It also gives less time complexity as compared to existing one. At the last stage comparing the time complexity for encryption and decryption process for all three types of input. This paper also demonstrates a side channel attack on the standard software implementation of the AES cryptographic algorithm.d