Hardware Precoding Demonstration in Multi-Beam UHTS Communications under Realistic Payload Characteristics

In this paper, we present a new hardware test-bed to demonstrate closed-loop precoded communications for interference mitigation in multi-beam ultra high throughput satellite systems under realistic payload and channel impairments. We build the test-bed to demonstrate a real-time channel aided precoded transmission under realistic conditions such as the power constraints and satellite-payload non-linearities. We develop a scalable architecture of an SDR platform with the DVB-S2X piloting. The SDR platform consists of two parts: analog-to-digital (ADC) and digital-to-analog (DAC) converters preceded by radio frequency (RF) front-end and Field-Programmable Gate Array (FPGA) backend. The former introduces realistic impairments in the transmission chain such as carrier frequency and phase misalignments, quantization noise of multichannel ADC and DAC and non-linearities of RF components. It allows evaluating the performance of the precoded transmission in a more realistic environment rather than using only numerical simulations. We benchmark the performance of the communication standard in realistic channel scenarios, evaluate received signal SNR, and measure the actual channel throughput using LDPC codes

Exploring HLS Coding Techniques to Achieve Desired Turbo Decoder Architectures

Software defined radio (SDR) platforms implement many digital signal processing algorithms. These can be accelerated on an FPGA to meet performance requirements. Due to the flexibility of SDR\u27s and continually evolving communications protocols, high level synthesis (HLS) is a promising alternative to standard handcrafted design flows. A crucial component in any SDR is the error correction codes (ECC). Turbo codes are a common ECC that are implemented on an FPGA due to their computational complexity. The goal of this thesis is to explore the HLS coding techniques required to produce a design that targets the desired hardware architecture and can reach handcrafted levels of performance. This work implemented three existing turbo decoder architectures with HLS to produce quality hardware which reaches handcrafted performance. Each targeted design was analyzed to determine its functionality and algorithm so a C implementation could be developed. Then the C code was modified and HLS directives were added to refine the design through the HLS tools. The process of code modification and processing through the HLS tools continued until the desired architecture and performance were reached. Each design was implemented and the bottlenecks were identified and dealt with through appropriate usage of directives and C style. The use of pipelining to bypass bottlenecks added a small overhead from the ramp-up and ramp-down of the pipeline, reducing the performance by at most 1.24%. The impact of the clock constraint set within the HLS tools was also explored. It was found that the clock period and resource usage estimate generated by the HLS tools is not accurate and all evaluations should occur after hardware synthesis

State of the art baseband DSP platforms for Software Defined Radio: A survey

Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities and industries to support SDR applications. This article presents an overview of current platforms and analyzes the related architectural choices, the current issues in SDR, as well as potential future trends.Peer reviewe

Fast Memory-Based Processing in Software-Defined Radios

Negli ultimi anni le Software Defined Radio sono state un argomento di ricerca di primo piano nell'ambito dei sistemi di trasmissione radio. Molti e variegati paradigmi implementativi sono stati concepiti e proposti, con soluzioni capaci di spaziare da sistemi basati su Field Programmable Gate Array (FPGA) a implementazioni ottenute mediante un singolo General Purpose Processor (GPP) passando per dispositivi caratterizzati dalla presenza computazionalmente preponderante di un Digital Signal Processor (DSP) o da architetture miste. Tali soluzioni rappresentano punti di equilibrio diversi dell'inevitabile compromesso tra flessibilità e capacità computazionale del sistema di trasmissione implementato, comprimendo in qualche modo l'aspirazione ad un sistema radio universale propria del concetto originario dell'SDR. A questo riguardo, le soluzioni SDR basate su GPP rappresentano il modello implementativo maggiormente desiderabile in quanto costituiscono l'alternativa più flessibile ed economica tra tutte le tipologie di SDR. Ciò nonostante, la scarsa capacità computazionale ha sempre limitato l'adozione di questi sistemi in scenari produttivi di vasta scala. Se convenientemente applicati entro il contesto di sviluppo SDR, concetti classici noti in informatica sotto la denominazione collettiva di space/time trade-off possono essere di enorme aiuto quando si cerchi di mitigare un simile problema. Traendo ispirazione da detti concetti, nonché estendendoli ed applicandoli all'abito dell'SDR, questa tesi sviluppa e presenta una tecnica di programmazione specifica per software radio chiamata Memory Acceleration (MA) che, mediante un uso estensivo delle risorse di memoria disponibili a bordo di un tipico sistema di calcolo general purpose, può fornire alle SDR convenzionali basate su GPP fattori di accelerazione sostanziali (circa un ordine di grandezza) senza ridurne la peculiare flessibilità. Alcune rilevanti implementazioni di sistemi SDR capaci di lavorare in tempo reale su processori GPP consumer-grade realizzate in tecnica MA sono descritte in dettaglio entro questo lavoro di tesi e fornite come prova della reale efficacia del concetto proposto

Practical Guidelines for Approaching the Implementation of Neural Networks on FPGA for PAPR Reduction in Vehicular Networks

Nowadays, the sensor community has become wireless, increasing their potential and applications. In particular, these emerging technologies are promising for vehicles' communications (V2V) to dramatically reduce the number of fatal roadway accidents by providing early warnings. The ECMA-368 wireless communication standard has been developed and used in wireless sensor networks and it is also proposed to be used in vehicular networks. It adopts Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) technology to transmit data. However, the large power envelope fluctuation of OFDM signals limits the power efficiency of the High Power Amplifier (HPA) due to nonlinear distortion. This is especially important for mobile broadband wireless and sensors in vehicular networks. Many algorithms have been proposed for solving this drawback. However, complexity and implementations are usually an issue in real developments. In this paper, the implementation of a novel architecture based on multilayer perceptron artificial neural networks on a Field Programmable Gate Array (FPGA) chip is evaluated and some guidelines are drawn suitable for vehicular communications. The proposed implementation improves performance in terms of Peak to Average Power Ratio (PAPR) reduction, distortion and Bit Error Rate (BER) with much lower complexity. Two different chips have been used, namely, Xilinx and Altera and a comparison is also provided. As a conclusion, the proposed implementation allows a minimal consumption of the resources jointly with a higher maximum frequency, higher performance and lower complexity.This work has been partly funded by projects TERESA-ADA (TEC2017-90093-C3-2-R) (MINECO/AEI/FEDER, UE) and ELISA (TEC2014-59255-C3-3-R)