2 research outputs found
FPGA implementation of a fault-tolerant application-specific NoC design
Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem is fatal to application-specific Network-on-Chip (NoC) designs as well if they cannot tolerate such failures. One solution to this problem can be having alternative routing options on the network for each communicating pair. In this study, we present an FPGA implementation of such a method for application-specific NoCs. This method adds additional network resources to the non-fault-tolerant design in an attempt to make it fault-tolerant. We show the effects of the presented fault-tolerant method on an FPGA implementation of Mp3 encoder based on energy consumption and area increase against non-fault-tolerant case. © 2016 IEEE
Fault-Tolerant Application-Specific Topology based NoC and its Prototype on an FPGA
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for
meeting current application requirements. Interconnection links are the primary components involved in
communication between the cores of an ASNoC design. The integration density in ASNoC increases with
continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the
formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant
techniques are required to address the permanent faults in interconnection links of an ASNoC design.
By taking into account link faults in the topology, this paper introduces a fault-tolerant application-specific
topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology,
a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link
faults into account in ASNoC design, we also propose an application mapping heuristic and a table-based
fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in
fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group
(MPEG) - 4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software
and hardware platforms. The static performance metric communication cost and the dynamic performance
metrics network latency, throughput, and router power consumption are examined using software platform.
In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed
fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization,
and power consumption. The results are compared with the existing approaches, specifically Ring topology
and its modified versions on both software and hardware platforms. The experimental results obtained from
software and hardware platforms for a specific link and any link fault show significant improvements in
performance metrics using our approach when compared with the related works in the literature.publishedVersio