Accelerated degradation modeling considering long-range dependence and unit-to-unit variability

Accelerated degradation testing (ADT) is an effective way to evaluate the reliability and lifetime of highly reliable products. Existing studies have shown that the degradation processes of some products are non-Markovian with long-range dependence due to the interaction with environments. Besides, the degradation processes of products from the same population generally vary from each other due to various uncertainties. These two aspects bring great difficulty for ADT modeling. In this paper, we propose an improved ADT model considering both long-range dependence and unit-to-unit variability. To be specific, fractional Brownian motion (FBM) is utilized to capture the long-range dependence in the degradation process. The unit-to-unit variability among multiple products is captured by a random variable in the degradation rate function. To ensure the accuracy of the parameter estimations, a novel statistical inference method based on expectation maximization (EM) algorithm is proposed, in which the maximization of the overall likelihood function is achieved. The effectiveness of the proposed method is fully verified by a simulation case and a microwave case. The results show that the proposed model is more suitable for ADT modeling and analysis than existing ADT models

A critical review of improved deep learning methods for the remaining useful life prediction of lithium-ion batteries.

As widely used for secondary energy storage, lithium-ion batteries have become the core component of the power supply system and accurate remaining useful life prediction is the key to ensure its reliability. Because of the complex working characteristics of lithium-ion batteries as well as the model parameter changing along with the aging process, the accuracy of the online remaining useful life prediction is difficult but urgent to be improved for the reliable power supply application. The deep learning algorithm improves the accuracy of the remaining useful life prediction, which also reduces the characteristic testing time requirement, providing the possibility to improve the power profitability of predictive energy management. This article analyzes, reviews, classifies, and compares different adaptive mathematical models on deep learning algorithms for the remaining useful life prediction. The features are identified for the modeling ability, according to which the adaptive prediction methods are classified. The specific criteria are defined to evaluate different modeling accuracy in the deep learning calculation procedure. The key features of effective life prediction are used to draw relevant conclusions and suggestions are provided, in which the high-accuracy deep convolutional neural network — extreme learning machine algorithm is chosen to be utilized for the stable remaining useful life prediction of lithium-ion batteries

Hierarchical fiber bundle strength statistics

Multi-scale modeling is currently one of the most active research topics in a wide range of disciplines. In this thesis we develop innovative hierarchical multi-scale models to analyze the probabilistic strength of fiber bundle structures. The Fiber Bundle Model (FBM) was developed initially by Daniels (1945), and then expanded, modified and generalized by many authors. Daniels considered a bundle of N fibers with identical elastic properties under uniform tensile stress. When a fiber breaks, the load from the broken fiber is distributed equally over all the remaining fibers (global load sharing). The strength of fibers is assigned randomly most often according to the Weibull probability distribution. In chapter 2, we develop for the first time an ad hoc hierarchical theory designed to tackle hierarchical architectures, thus allowing the determination of the strength of macroscopic hierarchical materials from the properties of their constituents at the nanoscale. The results show that the mean strength of the fiber bundle is reduced when scaling up from a fiber bundle to bundles of bundles. The hierarchical model developed in this study enables the prediction of strength values in good agreement with existing experimental results. This new ad hoc extension of the fiber bundle model is used for evaluating the role of hierarchy on structural strength. Different hierarchical architectures of fiber bundles have been investigated through analytical multiscale calculations based on a fiber bundle model at each hierarchical level. In general, we find that an increase in the number of hierarchical levels leads to a decrease in the strength of material. On a more abstract level, the hierarchical fiber bundle model (HFBM), an extension of the fiber bundle model (FBM) presented in this thesis, can be applied to any hierarchical system. FBMs are an established method helpful to understand hierarchical strength. Another extension of Daniels‘ theory for bimodal statistical strength has been implemented to model flaws in carbon nanotube fibers such as joints between carbon nanotubes, where careful analysis is necessary to assess the true mean strength. This model provides a more realistic description of the microscopic structure constituted by a nanotube-nanotube joint than a simple fiber bundle model. We demonstrate that the disorder distribution and the relative importance of the two failure modes have a substantial effect on mean strength of the structure. As mentioned, the fiber bundle model describes a collection of elastic fibers under load. The fibers fail successively and for each failure, the load is redistributed among the surviving fibers. In the fiber bundle model, the survival probability is defined as a ratio between number of surviving fibers and the total number of fibers in the bundle. We find that this classical relation is no longer suitable for a bundle with a small number of fibers, so that it is necessary to implement a modification into the probability function. It is possible to predict snap-back instabilities by inserting this modification in the theoretical expression of the load-strain (F-ε) relationship for the bundle, as discussed in chapter 4. Scrutiny into the composition of natural, or biological materials convincingly reveals that high material and structural efficiency can be attained, even with moderate-quality constituents, by hierarchical topologies, i.e., successively organized material levels. This is shown in chapter 5, where a composite bundle with two different types of fibers is considered, and an improvement in the mean strength is obtained for some specific hierarchical architectures, indicating that both hierarchy and material ―mixing‖ are necessary ingredients to obtain improved mechanical properties. In Chapter 6, we consider a novel modeling approach, namely we introduce self healing in a fiber bundle model. Here, we further assume that faile

Fractal Analysis of Microstructural and Fractograpghic Images for Evaluation of Materials

Materials have hierarchically organized complex structures at different length scales. Quantitative description of material behaviour is dependent on four fundamental length scales [1], which are of concern to materials scientists. These are (1) nano scale, 1-103 nm, (2)micro scale, 1-10 3 μm, (3) macro scale, 1-103mm, and (4) global size scale, 1-106 m. While the nano scale corresponds to, often, highly ordered atomic structures, the global size scale relates geophysical phenomena and large man made engineering structures. Micro scale and macro scale correspond to size of material samples used in laboratories, for designing and for fabrication of miniature to small machineries

Hardware runtime management for task-based programming models

Task-based programming models allow programmers to express applications as a collection of tasks with dependences. They are simple to use and greatly improve programmability by using software runtimes to exploit task parallelism and heterogeneity over multi-core, many-core and heterogeneous platforms. In these programming models, the runtimes guarantee correct execution order by managing tasks using task-dependence graphs (TDGs). These runtimes are powerful enough to provide high performance with coarse-grained tasks although they impose overheads on the application execution to maintain all the information they need to do their work. However, as the current trend in processor architectures keeps including more cores and heterogeneity (in fact complexity) in the systems, coarse-grained parallelism is not enough to feed all the underlying resources. Instead, fine-grained tasks are preferable as they are able to expose higher parallelism in applications but the overheads introduced by the software runtimes under these conditions prevent an efficient exploitation of fine-grained parallelism. The two most critical runtime overheads are task dependence graph management and task scheduling to heterogeneous systems. We propose a hardware architecture Picos, consisting of a hardware task dependence manager including nested task support, and a heterogeneous task scheduler, to accelerate the critical runtime functions for task-based programming models. With Picos, we aim at extending the benefit of these programming models into exploiting fine-grained task parallelism and heterogeneity. As a proof-of-concept, Three prototypes of Picos have been designed in VHDL and implemented in a System-on-chip platform consisting of regular ARM SMP cores and an integrated FPGA. They also have been analyzed with real benchmarks with OmpSs running and Linux on the platform. The first prototype is a hardware task dependence manager, which has been implemented in a Xilinx Zynq 7000 series SoCs. It is connected to a 2-core ARM Cortex A9 processor, with bare-metal OS integration. With 24 simulated workers, and running real task-dependence analysis in Picos, it scales up to 21x speedup. The second prototype Picos++ extended Picos with an exciting new feature for nested task support in hardware. To the best of our knowledge, this is the first time that such a feature has been support fully in hardware task dependence managers. This prototype is fully integrated in not only hardware, but also with a State-of-the-Art parallel programming model, and with Linux. The third prototype includes both a hardware task dependence manager and a heterogeneous task scheduler. The heterogeneous task scheduler receives ready tasks from the task-dependence manager and then schedule them to hardware execution units that have the estimated earliest finish time. It is implemented in a Xilinx Zynq Ultrascale+ MPSoC chip. In a system with 4 threads and up to 15 HW accelerators, it achieves up to 16.2x speedup for real benchmarks, and saves up to 90% of energy.Los modelos de programación basados en tareas permiten a los programadores expresar las aplicaciones como una colección de tareas con dependencias entre ellas. Dichos modelos son simples de usar y mejoran enormemente la programabilidad. Para ello se valen del uso de una runtime que en tiempo de ejecución ayuda a explotar el paralelismo de las tareas cuando se ejecutan en plataformas multi-cores, many-cores y heterogéneas. En estos modelos de programación los runtimes garantizan la ejecución de las tareas en el orden correcto mediante el uso de gráficos de dependencias entre tareas (TDG). Actualmente, los runtimes son lo suficientemente potentes para proporcionar un alto rendimiento con tareas de granularidad gruesa a pesar de que para mantener toda la información que necesitan para hacer su trabajo, introducen un sobrecoste importante en la ejecución de las aplicaciones. El problema viene dado por la tendencia actual en arquitectura de computadores a seguir incluyendo más núcleos y heterogeneidad (de hecho, complejidad) en los sistemas de procesado con lo que el paralelismo de granularidad gruesa no es suficiente para alimentar todos los recursos. En estos entornos complejos las tareas de granularidad fina son preferibles ya que son capaces de exponer un mayor paralelismo de las aplicaciones. Sin embargo, con tareas de granularidad fina, los sobrecostes introducidos por los runtimes software son mayores debido a la necesidad de manejar muchas más tareas más rápido. En general los mayores sobrecostes introducidos por los runtimes son: la administración de los grafos de dependencias que relacionan las tareas y la gestión de las tareas en sistemas heterogéneos. Proponemos una arquitectura hardware, llamada Picos, que consiste en un administrador de dependencias entre tareas incluyendo soporte para tareas anidadas y planificación de tareas heterogéneas. La función principal de dicha arquitectura es acelerar las funciones críticas de los runtimes para modelos de programación basados en tareas. Con Picos, se pretende extender el beneficio de estos modelos de programación para explotar el paralelismo y la heterogeneidad ejecutando tareas de granularidad fina. Como prueba de concepto, tres prototipos de Picos han sido diseñado en VHDL e implementado en una plataforma System-on-chip que consta de varios núcleos ARM integrados junto con una FPGA, y ademas analizados con ejecuciones reales con OmpSs y con Linux. El primer prototipo es un administrador hardware de tareas con dependencias, que se ha implementado en un SoC Xilinx Zynq serie 7000. Está conectado a un procesador ARM Cortex A9 de 2 núcleos, e integrado con el SO. Con 24 núcleos simulados y realizando el análisis real de las dependencias entre tareas en Picos, obtiene hasta un 21x sobre las mismas ejecuciones usando el entorno software. El segundo prototipo, Picos++, amplió Picos incorporando el soporte para la gestión de tareas anidadas en hardware. Hasta donde llega nuestro conocimiento, esta es la primera vez que dicha característica ha sido propuesta y/o incorporada en un administrador hardware de dependencias entre tareas. El segundo prototipo está completamente integrado en el sistema, no solo en hardware, sino también con el modelo de programación paralelo y con el sistema operativo. El tercer prototipo, incluye un administrador y planificador de tareas heterogéneas. El planificador de tareas heterogéneas recibe dichas tareas listas del administrador de dependencias entre tareas y las programa en la unidad de ejecución de hardware adecuada que tenga el tiempo de finalización estimado más corto. Este prototipo se ha implementado en un chip MPSoC Xilinx Zynq Ultrascale+. En dicho sistema con cuatro núcleos ARM y hasta 15 aceleradores HW funcionales, logra una aceleración de hasta 16.2x, y ahorra hasta el 90% de la energía con respecto al software.Postprint (published version

Hardware runtime management for task-based programming models

Task-based programming models allow programmers to express applications as a collection of tasks with dependences. They are simple to use and greatly improve programmability by using software runtimes to exploit task parallelism and heterogeneity over multi-core, many-core and heterogeneous platforms. In these programming models, the runtimes guarantee correct execution order by managing tasks using task-dependence graphs (TDGs). These runtimes are powerful enough to provide high performance with coarse-grained tasks although they impose overheads on the application execution to maintain all the information they need to do their work. However, as the current trend in processor architectures keeps including more cores and heterogeneity (in fact complexity) in the systems, coarse-grained parallelism is not enough to feed all the underlying resources. Instead, fine-grained tasks are preferable as they are able to expose higher parallelism in applications but the overheads introduced by the software runtimes under these conditions prevent an efficient exploitation of fine-grained parallelism. The two most critical runtime overheads are task dependence graph management and task scheduling to heterogeneous systems. We propose a hardware architecture Picos, consisting of a hardware task dependence manager including nested task support, and a heterogeneous task scheduler, to accelerate the critical runtime functions for task-based programming models. With Picos, we aim at extending the benefit of these programming models into exploiting fine-grained task parallelism and heterogeneity. As a proof-of-concept, Three prototypes of Picos have been designed in VHDL and implemented in a System-on-chip platform consisting of regular ARM SMP cores and an integrated FPGA. They also have been analyzed with real benchmarks with OmpSs running and Linux on the platform. The first prototype is a hardware task dependence manager, which has been implemented in a Xilinx Zynq 7000 series SoCs. It is connected to a 2-core ARM Cortex A9 processor, with bare-metal OS integration. With 24 simulated workers, and running real task-dependence analysis in Picos, it scales up to 21x speedup. The second prototype Picos++ extended Picos with an exciting new feature for nested task support in hardware. To the best of our knowledge, this is the first time that such a feature has been support fully in hardware task dependence managers. This prototype is fully integrated in not only hardware, but also with a State-of-the-Art parallel programming model, and with Linux. The third prototype includes both a hardware task dependence manager and a heterogeneous task scheduler. The heterogeneous task scheduler receives ready tasks from the task-dependence manager and then schedule them to hardware execution units that have the estimated earliest finish time. It is implemented in a Xilinx Zynq Ultrascale+ MPSoC chip. In a system with 4 threads and up to 15 HW accelerators, it achieves up to 16.2x speedup for real benchmarks, and saves up to 90% of energy.Los modelos de programación basados en tareas permiten a los programadores expresar las aplicaciones como una colección de tareas con dependencias entre ellas. Dichos modelos son simples de usar y mejoran enormemente la programabilidad. Para ello se valen del uso de una runtime que en tiempo de ejecución ayuda a explotar el paralelismo de las tareas cuando se ejecutan en plataformas multi-cores, many-cores y heterogéneas. En estos modelos de programación los runtimes garantizan la ejecución de las tareas en el orden correcto mediante el uso de gráficos de dependencias entre tareas (TDG). Actualmente, los runtimes son lo suficientemente potentes para proporcionar un alto rendimiento con tareas de granularidad gruesa a pesar de que para mantener toda la información que necesitan para hacer su trabajo, introducen un sobrecoste importante en la ejecución de las aplicaciones. El problema viene dado por la tendencia actual en arquitectura de computadores a seguir incluyendo más núcleos y heterogeneidad (de hecho, complejidad) en los sistemas de procesado con lo que el paralelismo de granularidad gruesa no es suficiente para alimentar todos los recursos. En estos entornos complejos las tareas de granularidad fina son preferibles ya que son capaces de exponer un mayor paralelismo de las aplicaciones. Sin embargo, con tareas de granularidad fina, los sobrecostes introducidos por los runtimes software son mayores debido a la necesidad de manejar muchas más tareas más rápido. En general los mayores sobrecostes introducidos por los runtimes son: la administración de los grafos de dependencias que relacionan las tareas y la gestión de las tareas en sistemas heterogéneos. Proponemos una arquitectura hardware, llamada Picos, que consiste en un administrador de dependencias entre tareas incluyendo soporte para tareas anidadas y planificación de tareas heterogéneas. La función principal de dicha arquitectura es acelerar las funciones críticas de los runtimes para modelos de programación basados en tareas. Con Picos, se pretende extender el beneficio de estos modelos de programación para explotar el paralelismo y la heterogeneidad ejecutando tareas de granularidad fina. Como prueba de concepto, tres prototipos de Picos han sido diseñado en VHDL e implementado en una plataforma System-on-chip que consta de varios núcleos ARM integrados junto con una FPGA, y ademas analizados con ejecuciones reales con OmpSs y con Linux. El primer prototipo es un administrador hardware de tareas con dependencias, que se ha implementado en un SoC Xilinx Zynq serie 7000. Está conectado a un procesador ARM Cortex A9 de 2 núcleos, e integrado con el SO. Con 24 núcleos simulados y realizando el análisis real de las dependencias entre tareas en Picos, obtiene hasta un 21x sobre las mismas ejecuciones usando el entorno software. El segundo prototipo, Picos++, amplió Picos incorporando el soporte para la gestión de tareas anidadas en hardware. Hasta donde llega nuestro conocimiento, esta es la primera vez que dicha característica ha sido propuesta y/o incorporada en un administrador hardware de dependencias entre tareas. El segundo prototipo está completamente integrado en el sistema, no solo en hardware, sino también con el modelo de programación paralelo y con el sistema operativo. El tercer prototipo, incluye un administrador y planificador de tareas heterogéneas. El planificador de tareas heterogéneas recibe dichas tareas listas del administrador de dependencias entre tareas y las programa en la unidad de ejecución de hardware adecuada que tenga el tiempo de finalización estimado más corto. Este prototipo se ha implementado en un chip MPSoC Xilinx Zynq Ultrascale+. En dicho sistema con cuatro núcleos ARM y hasta 15 aceleradores HW funcionales, logra una aceleración de hasta 16.2x, y ahorra hasta el 90% de la energía con respecto al software

Remote Sensing of the Aquatic Environments

The book highlights recent research efforts in the monitoring of aquatic districts with remote sensing observations and proximal sensing technology integrated with laboratory measurements. Optical satellite imagery gathered at spatial resolutions down to few meters has been used for quantitative estimations of harmful algal bloom extent and Chl-a mapping, as well as winds and currents from SAR acquisitions. The knowledge and understanding gained from this book can be used for the sustainable management of bodies of water across our planet