An Approach Combining Simulation and Verification for SysML using SystemC and Uppaal

International audienceEnsuring the correction of heterogeneous and complex systems is an essential stage in the process of engineering systems.In this paper we propose a methodology to verify and validate complex systems specified with SysML language using a combination of the two techniques of simulation and verification. We translate SysML specifications into SystemC models to validate the designed systems by simulation, then we propose to verify the derived SystemC models by using the Uppaal model checker. A case study is presented to demonstrate the effectiveness of our approach

Real-time VLSI architecture for bio-medical monitoring

This paper discusses the architecture and implementation of SSS2, a high-performance real-time signal processing system developed with a hybrid ESL/RTL methodology and targeted to biomedical image processing. Traditional methodologies, as well as new tools, such as Cebatech's C2R untimed-C synthesizer have been employed in the design of the system. The SSS2 platform specifies a parametric number of scalar processing elements, based on multiple 32-bit Sparc-compliant engines, augmented with LE2, an ESL-designed 2-way LIW/SIMD accelerator. LE2, which is purely designed in C, exposes a consistent interface to its SIMD datapath directly which is directly derived from the C-source of open-source image processing codes. It is synthesized to Verilog RTL with C2R. Behaviorally-synthesized SIMD datapaths are then 'plugged-in' into the exposed LE2 datapath interface. The LE2 memory interface can be either a cache- based configurable vector load/store unit or a multi-banked, multi-channel streaming local memory system. Results drawn from this work strongly suggest a shift towards a hybrid approach in designing multi-core systems for high bandwidth streaming and for dealing with large scale medical image transfers and non-linear bio-signal processing algorithms

UML as a system level design methodology with application to software radio

Master'sMASTER OF SCIENC

Application Domain-Driven System Design for Pervasive Video Processing

International audiencePervasive video processing in future Ambient Intelligence environments sets new challenges in embedded system design. In particular, very high performance requirements have to be combined with the constraints of deeply embedded systems, frequently changing operating modes, and low-cost, high-volume production. By leveraging upon the key properties of the application domain, we devised a computation model, a hardware template, and a programming approach which provide a natural mapping from application requirements to a complete system solution. Our approach enables the direct exploitation of concurrency and regularity in achieving the combined challenge of adaptability, performance, and efficiency

CarRing IV- Real-time Computer Network

Ob in der Automobil-, Avionik- oder Automatisierungstechnik, die Fortschritte in der Echtzeitkommunikation richten sich auf weitere Verbesserungen bereits existierender Lösungen. Im Kfz-Bereich führen die steigenden Zahlen computerbasierter Systeme, Anwendungen und Anschlüsse sowie die Verwendung mehrerer proprietärer Kommunikationsstandards zu einem immer komplexeren Kabelbaum. Ursächlich hierfür sind inkompatible Standards, wodurch nicht nur die Kosten, sondern auch das Gewicht und damit der Kraftstoffverbrauch negativ beeinflusst werden. Im ersten Teil der Dissertation wird das Echtzeitprotokoll von CarRing IV (CRIV) vorgestellt. Es bietet isochrone und harte Echtzeitgarantien, ohne dass eine netzwerkweite Synchronisation erforderlich ist. Mit bis zu 16 Knoten pro Ring kann ein CR-IV-Netz aus bis zu 256 Ringen bestehen, die durch Router miteinander verbunden sind. CR-IV verwendet ein reduziertes OSI-Modell (Schichten 1-3, 7), das für seine Anwendungsbereiche sowohl typisch als auch vorteilhaft ist. Außerdem unterstützt es sowohl ereignis- als auch zeitgesteuerte Kommunikationsparadigmen. Der Transparent-Modus ermöglicht es CR-IV, als Backbone für bestehende Netze zu verwenden, wodurch Inkompatibilitätsprobleme beseitigt werden und der Wechsel zu einer einheitlicheren Netzlösung erleichtert wird. Mit dieser Funktionalität können Nutzergeräte über ein CR-IV-Netz miteinander verbunden werden, ohne dass der Nutzer eingreifen oder etwas ändern muss. Durch Multicast unterstützt CRIV auch die Emulation von Feldbussen. Der zweite Teil der Dissertation stellt den anderen wichtigen Aspekt von CR-IV vor. Alle Schichten des OSI-Modells sind in einem FPGA mit Hardware Description Languages (HDLs) ohne Hard- oder Softprozessoren implementiert. Das Register-Transfer-Level (RTL)-Hardwaredesign von CR-IV wird mit einem neuen Ansatz erstellt, der am besten als tokenbasierter Datenfluss beschrieben werden kann. Der Ansatz ist sowohl vertikal als auch horizontal skalierbar. Er verwendet lose gekoppelte Processing Elements (PEs), die stateless arbeiten, sowie Arbiter/Speicherzuordnungspaare. Durch die granulare Kontrolle und die Aufteilung aller Aspekte einer Lösung eignet sich der Ansatz für die Implementierung anderer Software-Level-Lösungen in Hardware. Viele Testszenarios werden durchgeführt, um die in CR-IV erzielten Ergebnisse zu verdeutlichen und zu überprüfen. Diese Szenarien reichen von direkten Leistungsmessungen bis hin zu verhaltensspezifischen Tests. Zusätzlich wird eine Labor-Demo erstellt, die grundsätzlich auf ein Proof of Concept zielt. Die Demo stellt einen praktischen Test anstelle szenariospezifischer Tests dar. Alle Testszenarien und die Labor-Demo werden mit den Prototyp-Boards des Projekts durchgef¨uhrt, d.h. es sind keine Simulationstests. Die Ergebnisse stellen die realistischen Leistungen von CR-IV mit bis zu 13,61 Gbit/s dar.Whether be it automotive, avionics or automation, advances in their respective real-time communication technology focus on further improving preexisting solutions. For in-vehicle communication, the ever-increasing number of computer-based systems, applications and connections as well as the use of multiple proprietary communication standards results in an increasingly complex wiring harness. This is in-part due to those standards being incompatible with one another. In addition to cost, this also impacts weight, which in turn affects fuel consumption. The work presented in this thesis is in-part theoretical and in-part applied. The former is represented by a new protocol, while the latter corresponds to the protocol’s hardware implementation. In the first part of the thesis, the real-time communication protocol of CarRing IV (CR-IV) is presented. It provides isochronous and hard real-time guarantees without requiring network-wide clock synchronization. With up to 16 nodes per ring, a CR-IV network can consist of as many as 256 rings interconnected by routers. CR-IV uses a reduced OSI model (layers 1-3, 7), which is both typical of and preferable for its application areas. Moreover, it supports both event- and time-triggered communication paradigms. The transparent mode feature allows CR-IV to act as a backbone for existing networks, thereby addressing incompatibility concerns and easing the transition into a more unified network solution. Using this feature, user devices can communicate with one another via a CR-IV network without requiring user interference, or any user device or application changes. Combined with the protocol’s reliable multicast, the feature extends CR-IV’s capabilities to include field bus emulation. The second part of the thesis presents the other important aspect of CR-IV. All of its OSI model layers are implemented in a FPGA using Hardware Description Languages (HDLs) without relying-on or including any hard or soft processors. CR-IV’s Register-Transfer Level (RTL) hardware design is created using a new approach that can best be described as token-based data-flow. The approach is both vertically and horizontally scalable. It uses stateless and loosely coupled Processing Elements (PEs) as well as arbiter/memory allocation pairs. By having granular control and compartmentalizing every aspect of a solution, the approach lends itself to being used for implementing other software-level solutions in hardware. Many test scenarios are conducted to both highlight and examine the results achieved in CR-IV. Those scenarios range from direct performance measurements to behavior-specific tests. Moreover, a lab-demo is created that essentially amounts to a proof of concept. The demo represents a practical test as opposed to a scenariospecific one. Whether be it test scenarios or the lab-demo, all are carried-out using the project’s prototype boards, i.e. no simulation tests. The results obtained represent CR-IV’s real-world realistic outcomes with up to 13.61 Gbps

Semantic Multi-View model for Low-Power

5 pagesNational audiencePower is an important concern in embedded systems. Reduction of power consumption is achieved by balancing the control of multiple domains: switching power, reducing or increasing voltage and changing the frequency on system sections. Model-Driven Engineering gives tools to model the interactions of these domains. In this work, we propose to use MARTE combined to UPF concepts to capture the structure and behavior of these multiple domains. We adopt CCSL to unify the multiform aspects among domains and to verify their proper interaction. We provide an example to illustrate MARTE representation and a simulation of multi-domain power design, specified on CCSL and running on TIMESQUARE