Exploiting temporal locality in drowsy cache policies

Technology projections indicate that static power will become a major concern in future generations of high-performance microprocessors. Caches represent a significant percentage of the overall microprocessor die area. Therefore, recent research has concentrated on the reduction of leakage current dissipated by caches. The variety of techniques to control current leakage can be classified as non-state preserving or state preserving. Non-state preserving techniques power off selected cache lines while state preserving place selected lines into a low-power state. Drowsy caches are a recently proposed state-preserving technique. In order to introduce low performance overhead, drowsy caches must be very selective on which cache lines are moved to a drowsy state. Past research on cache organization has focused on how best to exploit the temporal locality present in the data stream. In this paper we propose a novel drowsy cache policy called Reuse Most Recently used On (RMRO), which makes use of reuse information to trade off performance versus energy consumption. Our proposal improves the hit ratio for drowsy lines by about 67%, while reducing the power consumption by about 11.7% (assuming 70nm technology) with respect to previously proposed drowsy cache policies

Drowsy Cache Partitioning for Multithreaded Systems and High Level Caches

Power consumption is becoming an increasingly important component of processor design. As technology shrinks both static and dynamic power become more relevant. This is particularly important for the cache hierarchy. The cache portion of a microprocessor contains a large percentage of the total number of transistors in the microprocessor. Therefore the cache consumes a large percentage of both static and dynamic power. When improving power consumption in the past, there has always been a large trade-off between energy savings and performance. Techniques that reduce power consumption typically have a negative impact on performance. Likewise, when performance is improved it is at the cost of higher energy consumption. Also many current implementations only reduce one kind of power in the cache, either static or dynamic. For a more robust approach that will remain relevant as technology continues to shrink, both aspects of power need to be addressed. This thesis implements a phase adaptive cache that will reduce both static and dynamic power while having very little impact on the performance. This cache stores the most recently used blocks in one partition that is quick and easy to access. The second partition is placed in drowsy mode to reduce leakage power consumption. In this work, this approach is implemented for all three levels of cache in a multicore architecture. The design is also tested with multithreaded simulations. The results are measured using an architecture simulator. Simulations of the modified cache structure are compared to those of a baseline unchanged cache hierarchy running on the same machine. These results are compared for both energy savings including static and dynamic power, along with the overall impact on performance. The results in this work show that this cache design produces both dynamic energy and leakage energy savings with a low performance impact

A survey of emerging architectural techniques for improving cache energy consumption

The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students

Fast speculative address generation and way caching for reducing L1 data cache energy

L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access latency can be affected as well, leading to an increase in overall energy consumption due to increased execution time. At the same time, the static energy consumption of the cache increases significantly with each new process generation. This paper proposes a new approach to reduce the overall L1 cache energy consumption using a combination of way caching and fast, speculative address generation. A 16-entry way cache storing a 3-bit way number for recently accessed L1 data cache lines is shown sufficient to significantly reduce both static and dynamic energy consumption of the L1 cache. Fast speculative address generation helps to hide the way cache access latency and is highly accurate. The L1 cache energy-delay product is reduced by 10% compared to using the way cache alone and by 37% compared to the use of multiple MRU technique.Peer ReviewedPostprint (published version

A low-power cache system for high-performance processors

制度:新 ; 報告番号:甲3439号 ; 学位の種類:博士(工学) ; 授与年月日:12-Sep-11 ; 早大学位記番号:新576

Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy

Power consumption in computing today has lead the industry towards energy efficient computing. As transistor technology shrinks, new techniques have to be developed to keep leakage current, the dominant portion of overall power consumption, to a minimum. Due to the large amount of transistors devoted to the cache hierarchy, the cache provides an excellent avenue to dramatically reduce power usage. The inherent danger with techniques that save power can negatively effect the primary reason for the inclusion of the cache, performance. This thesis work proposes a modification to the cache hierarchy that dramatically saves power with only a slight reduction in performance. By taking advantage of the overwhelming preference of memory accesses to the most recently used blocks, these blocks are placed into a small, fast access A partition. The rest of the cache is put into a drowsy mode, a state preserving technique that reduces leakage power within the remaining portion of the cache. This design was implemented within a private, second level cache that achieved an average of almost 20% dynamic energy savings and an average of nearly 45% leakage energy savings. These savings were attained while incurring an average performance penalty of only 2%

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