OXIDATION OF SILICON - THE VLSI GATE DIELECTRIC

Silicon dominates the semiconductor industry for good reasons. One factor is the stable, easily formed, insulating oxide, which aids high performance and allows practical processing. How well can these virtues survive as new demands are made on integrity, on smallness of feature sizes and other dimensions, and on constraints on processing and manufacturing methods? These demands make it critical to identify, quantify and predict the key controlling growth and defect processes on an atomic scale.The combination of theory and novel experiments (isotope methods, electronic noise, spin resonance, pulsed laser atom probes and other desorption methods, and especially scanning tunnelling or atomic force microscopies) provide tools whose impact on models is just being appreciated. We discuss the current unified model for silicon oxidation, which goes beyond the traditional descriptions of kinetic and ellipsometric data by explicitly addressing the issues raised in isotope experiments. The framework is still the Deal-Grove model, which provides a phenomenology to describe the major regimes of behaviour, and gives a base from which the substantial deviations can be characterized. In this model, growth is limited by diffusion and interfacial reactions operating in series. The deviations from Deal-Grove are most significant for just those first tens of atomic layers of oxide which are critical for the ultra-thin oxide layers now demanded. Several features emerge as important. First is the role of stress and stress relaxation. Second is the nature of the oxide closest to the Si, both its defects and its differences from the amorphous stoichiometric oxide further out, whether in composition, in network topology, or otherwise. Thirdly, we must consider the charge states of both fixed and mobile species. In thin films with very different dielectric constants, image terms can be important; these terms affect interpretation of spectroscopies, the injection of oxidant species and relative defect stabilities. This has added importance now that P-b concentrations have been correlated with interfacial stress. This raises further issues about the perfection of the oxide random network and the incorporation of interstitial species like molecular oxygen.Finally, the roles of contamination, particles, metals, hydrocarbons etc are important, as is interface roughness. These features depend on pre-gate oxide cleaning and define the Si surface that is to be oxidized which may have an influence on the features listed above

Electrical overstress and electrostatic discharge failure in silicon MOS devices

This thesis presents an experimental and theoretical investigation of electrical failure in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with an extensive survey of MOS technology, its failure mechanisms and protection schemes. A program of experimental research on MOS breakdown is then reported, the results of which are used to develop a model of breakdown across a wide spectrum of time scales. This model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct use of causal theory over short time-scales, invalidating earlier theories on the subject. The work is extended to ESD stress of both polarities. Negative polarity ESD breakdownis found to be primarily oxide-voltage activated, with no significant dependence on temperature of luminosity. Positive polarity breakdown depends on the rate of surface inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced carriers. An analytical model, based upon the above theory is developed to predict ESD breakdown over a wide range of conditions. The thesis ends with an experimental and theoretical investigation of the effects of ESD breakdown on device and circuit performance. Breakdown sites are modelled as resistive paths in the oxide, and their distorting effects upon transistor performance are studied. The degradation of a damaged transistor under working stress is observed, giving a deeper insight into the latent hazards of ESD damage

Surface Potential Modelling of Hot Carrier Degradation in CMOS Technology

abstract: The scaling of transistors has numerous advantages such as increased memory density, less power consumption and better performance; but on the other hand, they also give rise to many reliability issues. One of the major reliability issue is the hot carrier injection and the effect it has on device degradation over time which causes serious circuit malfunctions. Hot carrier injection has been studied from early 1980's and a lot of research has been done on the various hot carrier injection mechanisms and how the devices get damaged due to this effect. However, most of the existing hot carrier degradation models do not consider the physics involved in the degradation process and they just calculate the change in threshold voltage for different stress voltages and time. Based on this, an analytical expression is formulated that predicts the device lifetime. This thesis starts by discussing various hot carrier injection mechanisms and the effects it has on the device. Studies have shown charges getting trapped in gate oxide and interface trap generation are two mechanisms for device degradation. How various device parameters get affected due to these traps is discussed here. The physics based models such as lucky hot electron model and substrate current model are presented and gives an idea how the gate current and substrate current can be related to hot carrier injection and density of traps created. Devices are stressed under various voltages and from the experimental data obtained, the density of trapped charges and interface traps are calculated using mid-gap technique. In this thesis, a simple analytical model based on substrate current is used to calculate the density of trapped charges in oxide and interface traps generated and it is a function of stress voltage and stress time. The model is verified against the data and the TCAD simulations. Finally, the analytical model is incorporated in a Verilog-A model and based on the surface potential method, the threshold voltage shift due to hot carrier stress is calculated.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Origin of trap assisted tunnelling in ammonia annealed SiC trench MOSFETs

The interface between silicon carbide (SiC) and silicon dioxide (SiO2) is of considerable importance for the performance and reliability of 4H-SiC (trench) metal oxide semiconductor field effect transistors (MOSFETs) and various different post oxidation anneals (POAs) have been used to optimize its quality. Whereas nitric oxide (NO) POA leads to very reliable and well performing MOSFETs, ammonia (NH3) can further improve the device performance, however, at the cost of the gate oxide (GOX) reliability, e.g. leading to trap assisted tunneling (TAT). We investigate the origin of TAT and GOX leakage in differently annealed gate oxides experimentally, using 4H-SiC trench MOSFETs, and theoretically, using Density Functional Theory (DFT) simulations. Our findings reinforce the view that the NO anneal for SiC devices results in the best overall quality as devices annealed in NH3 and nitrogen N2 show higher oxide charge density and leakage currents. DFT simulations demonstrate that, contrary to what has often been assumed so far, NH3 annealing leads to the formation of additional hydrogen related defects, which open leakage paths in the oxide otherwise not present in NO treated oxides

Relaxation and the nature of electrical stress related defects in ultra-thin dioxide on silicon

The instability of defects created in ultra-thin insulator, metal-oxide-silicon devices biased in the direct tunnel regime is investigated. For the case of electron injection from the silicon substrate, nearly complete defect relaxation is observed after the bias is removed, allowing the possibility of re-generating the defects. Modeling the defect generation process and examining differences between initial and subsequent degradation periods lead to an improved picture of both the relaxation process and the nature of the involved defects

Time domain analysis of switching transient fields in high voltage substations

Switching operations of circuit breakers and disconnect switches generate transient currents propagating along the substation busbars. At the moment of switching, the busbars temporarily acts as antennae radiating transient electromagnetic fields within the substations. The radiated fields may interfere and disrupt normal operations of electronic equipment used within the substation for measurement, control and communication purposes. Hence there is the need to fully characterise the substation electromagnetic environment as early as the design stage of substation planning and operation to ensure safe operations of the electronic equipment. This paper deals with the computation of transient electromagnetic fields due to switching within a high voltage air-insulated substation (AIS) using the finite difference time domain (FDTD) metho

Near infra-red single-photon detection using Ge-on-Si heterostructures

This Thesis investigates the design of Ge-on-Si single-photon avalanche diode (SPAD) detectors combining the many advantages of low-noise Si single-photon avalanche multiplication with the infrared sensing capability of germanium. The devices were simulated by using electric field modelling software to predict key aspects of the device behaviour in terms of the current-voltage characteristic and electric field. The devices were then characterised in terms of their single-photon performance. A 25 m diameter device showed a single-photon detection efficiency of ~ 4 % at a wavelength of 1310 nm and a temperature of 100 K when biased at 10 % above the breakdown voltage. In the same condition, a dark count rate of ~ 6 Mcs-1 was measured. This resulted in the lowest noise equivalent power of ~ 1 × 10-14 WHz-1/2 of Ge-on-Si SPADs reported in the scientific literature. At the longer wavelength of 1550 nm, the single-photon detection efficiency was reduced to ~ 0.1 % at 125 K and 6 % of relative excess bias. Although further investigation needs to be carried out, a potential major advantage of these devices compared to the InGaAs/InP SPADs could be that of reduced afterpulsing since a small increase (a factor of 2) in the normalised dark count rate was measured when the repetition rate was increased from 1 kHz to 1 MHz. Finally, the fill-factor enhancement of 32 × 32 Si CMOS SPAD arrays resulting from the integration of high efficiency diffractive optical microlens arrays was investigated. A full characterisation of SPAD arrays integrating microlens arrays in terms of improvement factor and spatial uniformity of detection is presented for the first time in the scientific literature in a large spectral range (500-900 nm) and different f-numbers (from f/2 to f/22) by using a double telecentric imaging system. The highest improvement factor of ~16 was measured for a SPAD array integrating microlens arrays, combined with a very high spatial efficiency uniformity of between 2–6%

Gate oxide failure in MOS devices

The thesis presents an experimental and theoretical investigation of gate oxide breakdown in MOS networks, with a particular emphasis on constant voltage overstress failure. It begins with a literature search on gate oxide failure mechanisms, particularly time-dependent dielectric breakdown, in MOS devices. The experimental procedure is then reported for the study of gate oxide breakdown under constant voltage stress. The experiments were carried out on MOSFETs and MOS capacitor structures, recording the characteristics of the devices before and after the stress. The effects of gate oxide breakdown in one of the transistors in an nMOS inverter were investigated and several parameters were found to have changed. A mathematical model for oxide breakdown, based on physical mechanisms, is proposed. Both electron and hole trapping occurred during the constant voltage stress. Breakdown appears to take place when the trapped hole density reach a critical value. PSPICE simulations were performed for the MOSFETs, nMOS inverter and CMOS logic circuits. Two models of MOSFET with gate oxide short were validated. A good agreement between experiments and simulations was achieved