On Firehoses, Windows, and Business Rules: Towards a Successful Fast Data Organisation

Due to the enormous growth of data and the increasing speed at which organisations are required to respond to it, Fast data is the latest trend in data science. In this study, we set out to answer the question what Fast data is and how organisations can deal with it in a successful way. We define Fast data as: the ability to gain insights from (near) real-time data streams and derive value from these insights. We argue that successful Fast data organisations are built on four pillars: (i) technology, (ii) strategy, (iii) culture, and (iv) skills & experience. We conclude with a critical discussion of our results, for instance touching upon whether Fast data is really ‘new’

Neuromorphic LIF Row-by-Row Multiconvolution Processor for FPGA

Deep Learning algorithms have become state-of-theart methods for multiple fields, including computer vision, speech recognition, natural language processing, and audio recognition, among others. In image vision, convolutional neural networks (CNN) stand out. This kind of network is expensive in terms of computational resources due to the large number of operations required to process a frame. In recent years, several frame-based chip solutions to deploy CNN for real time have been developed. Despite the good results in power and accuracy given by these solutions, the number of operations is still high, due the complexity of the current network models. However, it is possible to reduce the number of operations using different computer vision techniques other than frame-based, e.g., neuromorphic event-based techniques. There exist several neuromorphic vision sensors whose pixels detect changes in luminosity. Inspired in the leaky integrate-and-fire (LIF) neuron, we propose in this manuscript an event-based field-programmable gate array (FPGA) multiconvolution system. Its main novelty is the combination of a memory arbiter for efficient memory access to allowrow-by-rowkernel processing. This system is able to convolve 64 filters across multiple kernel sizes, from 1 × 1 to 7 × 7, with latencies of 1.3 μs and 9.01 μs, respectively, generating a continuous flow of output events. The proposed architecture will easily fit spike-based CNNs.Ministerio de Economía y Competitividad TEC2016-77785-

Continuous-time acquisition of biosignals using a charge-based ADC topology

This paper investigates continuous-time (CT) signal acquisition as an activity-dependent and nonuniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by nonuniform quantisation to commonly recorded biological signal fragments allowing a compression ratio of ≈5 and 26 when applied to electrocardiogram and extracellular action potential signals, respectively. We describe several desirable properties of CT sampling, including bandwidth reduction, elimination/reduction of quantisation error, and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT analogue-to-digital converter that has been optimized for the acquisition of neural signals. This has been implemented in a commercially available 0.35 μm CMOS technology occupying a compact footprint of 0.12 mm 2 . Silicon verified measurements demonstrate an 8-bit resolution and a 4 kHz bandwidth with static power consumption of 3.75 μW from a 1.5 V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39 pJ energy per conversion

Real-time Event-based Energy Metering

Real-time knowledge about the energy being exchanged sustains energy efficiency applications and services. The event-based data-saving approach to the measurements of electric energy has emerged recently with conceptual and practical implications, also thanks to the manufacturing of a new technological solution. This paper explains the fundamental underlying concepts that have led to these improvements through real-case examples. This work borrows from ontology the distinction between the concepts of endurants and perdurants, associating these concepts to the quantities involved in the energy metering process. In the new event-based computational framework, energy metering is interpreted by detecting average power and accumulated energy variations, as well as highlighting the importance of the information provided by the rate of change of energy and by the rate of events gathered from meters

Value of Information in Feedback Control: Quantification

Although transmission of a data packet containing sensory information in a networked control system improves the quality of regulation, it has indeed a price from the communication perspective. It is, therefore, rational that such a data packet be transmitted only if it is valuable in the sense of a cost-benefit analysis. Yet, the fact is that little is known so far about this valuation of information and its connection with traditional event-triggered communication. In the present article, we study this intrinsic property of networked control systems by formulating a rate-regulation trade-off between the packet rate and the regulation cost with an event trigger and a controller as two distributed decision makers, and show that the valuation of information is conceivable and quantifiable grounded on this trade-off. In particular, we characterize an equilibrium in the rate-regulation trade-off, and quantify the value of information VoIk there as the variation in a so-called value function with respect to a piece of sensory information that can be communicated to the controller at each time k. We prove that, for a multi-dimensional Gauss--Markov process, VoIk is a symmetric function of the discrepancy between the state estimates at the event trigger and the controller, and that a data packet containing sensory information at time k should be transmitted to the controller only if VoIk is nonnegative. Moreover, we discuss that VoIk can be computed with arbitrary accuracy, and that it can be approximated by a closed-form quadratic function with a performance guarantee

Accuracy-Energy Configurable Sensor Processor and IoT Device for Long-Term Activity Monitoring in Rare-Event Sensing Applications

A specially designed sensor processor used as a main processor in IoT (internet-of-thing) device for the rare-event sensing applications is proposed. The IoT device including the proposed sensor processor performs the event-driven sensor data processing based on an accuracy-energy configurable event-quantization in architectural level. The received sensor signal is converted into a sequence of atomic events, which is extracted by the signal-to-atomic-event generator (AEG). Using an event signal processing unit (EPU) as an accelerator, the extracted atomic events are analyzed to build the final event. Instead of the sampled raw data transmission via internet, the proposed method delays the communication with a host system until a semantic pattern of the signal is identified as a final event. The proposed processor is implemented on a single chip, which is tightly coupled in bus connection level with a microcontroller using a 0.18 μm CMOS embedded-flash process. For experimental results, we evaluated the proposed sensor processor by using an IR- (infrared radio-) based signal reflection and sensor signal acquisition system. We successfully demonstrated that the expected power consumption is in the range of 20% to 50% compared to the result of the basement in case of allowing 10% accuracy error

Design and Optimization of Low-power Level-crossing ADCs

This thesis investigates some of the practical issues related to the implementation of level-crossing ADCs in nanometer CMOS. A level-crossing ADC targeting minimum power is designed and measured. Three techniques to circumvent performance limitations due to the zero-crossing detector at the heart of the ADC are proposed and demonstrated: an adaptive resolution algorithm, an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130 nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5 uW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing sampling, namely SNDR higher than the classic Nyquist limit