Power Reduction Techniques in Clock Distribution Networks with Emphasis on LC Resonant Clocking

In this thesis we propose a set of independent techniques in the overall concept of LC resonant clocking where each technique reduces power consumption and improve system performance. Low-power design is becoming a crucial design objective due to the growing demand on portable applications and the increasing difficulties in cooling and heat removal. The clock distribution network delivers the clock signal which acts as a reference to all sequential elements in the synchronous system. The clock distribution network consumes a considerable amount of power in synchronous digital systems. Resonant clocking is an emerging promising technique to reduce the power of the clock network. The inductor used in resonant clocking enables the conversion of the electric energy stored on the clock capacitance to magnetic energy in the inductor and vice versa. In this thesis, the concept of the slack in the clock skew has been extended for an LC fully-resonant clock distribution network. This extra slack in comparison to standard clock distribution networks can be used to reduce routing complexity, achieve reduction in wire elongation, total wire length, and power consumption. Simulation results illustrate that by utilizing the proposed approach, an average reduction of 53% in the number of wire elongations and 11% reduction in total wire length can be achieved. A dual-edge clocking scheme introduced in the literature to enable the operation of the flip-flop at the rising- and falling edges of the clock has been modified. The interval by which the charging elements in the flip-flop are being switched-on was reduced causing a reduction in power consumption. Simulating the flip-flop in STMicroelectronics 90-nm technology shows correct functionality of the Sense Amplifier flip-flop with a resonant clock signal of 500 MHz and a throughput of 1 GHz under process, voltage, and temperature (PVT) variations. Modeling the resonant system with the proposed flip-flop illustrates that dual-edge compared to single-edge triggering can achieve up to 58% reduction in power consumption when the clock capacitance is the dominating factor. The application of low-swing clocking to LC resonant clock distribution network has been investigated on-chip. The proposed low-swing resonant clocking scheme operates with one voltage supply and does not require an additional supply voltage. The Differential Conditional Capturing flip-flop introduced in the literature was modified to operate with a low-swing sinusoidal clock. Low-swing resonant clocking achieved around 5.8% reduction in total power with 5.7% area overhead. Modeling the clock network with the proposed flip-flop illustrates that low-swing clocking can achieve up to 58% reduction in the power consumption of the resonant clock. An analytical approach was introduced to estimate the required driver strength in the clock generator. Using the proposed approach early in the design stage reduces area and power overhead by eliminating the need for programmable switches in the driving circuit

Power Reductions with Energy Recovery Using Resonant Topologies

The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3× the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR

Index to NASA Tech Briefs, 1975

This index contains abstracts and four indexes--subject, personal author, originating Center, and Tech Brief number--for 1975 Tech Briefs

Design and Test of a Gate Driver with Variable Drive and Self-Test Capability Implemented in a Silicon Carbide CMOS Process

Discrete silicon carbide (SiC) power devices have long demonstrated abilities that outpace those of standard silicon (Si) parts. The improved physical characteristics allow for faster switching, lower on-resistance, and temperature performance. The capabilities unleashed by these devices allow for higher efficiency switch-mode converters as well as the advance of power electronics into new high-temperature regimes previously unimaginable with silicon devices. While SiC power devices have reached a relative level of maturity, recent work has pushed the temperature boundaries of control electronics further with silicon carbide integrated circuits. The primary requirement to ensure rapid switching of power MOSFETs was a gate drive buffer capable of taking a control signal and driving the MOSFET gate with high current required. In this work, the first integrated SiC CMOS gate driver was developed in a 1.2 μm SiC CMOS process to drive a SiC power MOSFET. The driver was designed for close integration inside a power module and exposure to high temperatures. The drive strength of the gate driver was controllable to allow for managing power MOSFET switching speed and potential drain voltage overshoot. Output transistor layouts were optimized using custom Python software in conjunction with existing design tool resources. A wafer-level test system was developed to identify yield issues in the gate driver output transistors. This method allowed for qualitative and quantitative evaluation of transistor leakage while the system was under probe. Wafer-level testing and results are presented. The gate driver was tested under high temperature operation up to 530 degrees celsius. An integrated module was built and tested to illustrate the capability of the gate driver to control a power MOSFET under load. The adjustable drive strength feature was successfully demonstrated

A high-voltage pulsed power modulator for fast-rising arbitrary waveforms

This work presents the design and testing of a new semiconductor-based pulsed power modulator meeting the challenging requirements of a pulsed electron beam device (GESA): a fast-rising (10^12 V/s) output voltage with arbitrary waveform of maximum 120 kV at a maximum current of 600 A for a pulse duration of up to 100 µs

Development of reliability methodology for systems engineering. Volume II - Application - Design reliability analysis of a 250 volt-ampere static inverter Final report

Design stage reliability analysis application to static inverte

Development of limb volume measuring system

The mechanisms underlying the reductions in orthostatic tolerance associated with weightlessness are not well established. Contradictory results from measurements of leg volume changes suggest that altered venomotor tone and reduced blood flow may not be the only contributors to orthostatic intolerance. It is felt that a more accurate limb volume system which is insensitive to environmental factors will aid in better quantification of the hemodynamics of the leg. Of the varous limb volume techniques presently available, the ultrasonic limb volume system has proven to be the best choice. The system as described herein is free from environmental effects, safe, simple to operate and causes negligible radio frequency interference problems. The segmental ultrasonic ultrasonic plethysmograph is expected to provide a better measurement of limb volume change since it is based on cross-sectional area measurements

EMI measurement and modeling techniques for complex electronic circuits and modules

This dissertation consists of four papers. In the first paper, a combined model for predicting the most critical radiated emissions and total radiated power due to the display signals in a TV by incorporating the main processing board using the Huygens Equivalence theorem and the radiation due to the flex cable based on active probe measurements was developed. In the second paper, a frequency-tunable resonant magnetic field probe was designed in the frequency range 900-2260 MHz for near-field scanning applications for the radio frequency interference studies by using a varactor diode providing the required capacitance and the parasitic inductance of a magnetic field loop (i.e., a parallel LC circuit). Measurement results showed good agreement with the simulated results. In the third paper, a wideband microwave method was developed as a means for rapid detection of slight dissimilarities (including counterfeit) and aging effects in integrated circuits (ICs) based on measuring the complex reflection coefficient of an IC when illuminated with an open-ended rectangular waveguide probe, at K-band (18-26.5 GHz) and Ka-band (26.5-40 GHz) microwave frequencies. In the fourth paper, a method to predict radiated emissions from DC-DC converters with cables attached on the input side to a LISN and on the output side to a DC brushless motor as load based on linear terminal equivalent circuit modeling was demonstrated. The linear terminal equivalent model was extracted using measured input and output side common mode currents for various characterization impedances connected at the input and output terminals of the converter --Abstract, page iv

INVESTIGATION INTO SUBMICRON TRACK POSITIONING AND FOLLOWING TECHNOLOGY FOR COMPUTER MAGNETIC DISKS

In the recent past some magnetic heads with submicron trackwidth have been developed in order to increase track density of computer magnetic disks, however a servo control system for a submicron trackwidth head has not been investigated. The main objectives of this work are to investigate and develop a new servo pattern recording model, a new position sensor, actuator, servo controller used for submicron track positioning and following on a computer hard disk with ultrahigh track density, to increase its capacity. In this position sensor study, new modes of reading and writing servo information for longitudinal and perpendicular magnetic recording have been developed. The read/write processes in the model have been studied including the recording trackwidth, the bit length, the length and shape of the transition, the relationship between the length of the MR head and the recording wavelength, and the SIN of readout. lt has also been investigated that the servo patterns are magnetized along the radial direction by a transverse writing head that is aligned at right angles with the normal data head and the servo signals are reproduced by a transverse MR head with its stripe and pole gap tangential to the circumferential direction. lt has been studied how the servo signal amplitude and linearity are affected by the length of the MR sensor and the distance between the shields of the head. Such things as the spacing and length of the servo-pattern elements have been optimised so as to achieve minimum jitter and maximum utilisation of the surface of the disk. The factors (i.e. the skew angle of the head) affecting the SIN of the position sensor have been analysed and demonstrated. As a further development, a buried servo method has been studied which uses a servo layer underneath the data layer, so that a continuous servo signal is obtained. A new piezo-electric bimorph actuator has been demonstrated. This can be used as a fine actuator in hard disk recording. The linearity and delay of its response are improved by designing a circuit and selecting a dimension of the bimorph element. A dual-stage actuator has been developed. A novel integrated fine actuator using a piezo-electric bimorph has also been designed. A new type of construction for a magnetic head and actuator has been studied. A servo controller for a dual-stage actuator has been developed. The wholly digital controller for positioning and following has been designed and its performances have been simulated by the MAL TAB computer program. A submicron servo track writer and a laser system measuring dynamic micro-movement of a magnetic head have been specially developed for this project. Finally, track positioning and following on 0.7 µm tracks with a 7% trackwidth rms runout has been demonstrated using the new servo method when the disk-was rotating at low speed. This is one of the best results in this field in the world