On the Capacity of Multilevel NAND Flash Memory Channels

In this paper, we initiate a first information-theoretic study on multilevel NAND flash memory channels with intercell interference. More specifically, for a multilevel NAND flash memory channel under mild assumptions, we first prove that such a channel is indecomposable and it features asymptotic equipartition property; we then further prove that stationary processes achieve its information capacity, and consequently, as its order tends to infinity, its Markov capacity converges to its information capacity; eventually, we establish that its operational capacity is equal to its information capacity. Our results suggest that it is highly plausible to apply the ideas and techniques in the computation of the capacity of finite-state channels, which are relatively better explored, to that of the capacity of multilevel NAND flash memory channels.Comment: Submitted to IEEE Transactions on Information Theor

Анализ эффективности каскадного кодирования для повышения выносливости многоуровневой NAND флеш-памяти

Повышение плотности записи в современных чипах NAND флеш-памяти, достигаемое как за счет уменьшающегося физического размера ячейки, так и благодаря возрастающему количеству используемых состояний ячейки, сопровождается снижением надежности хранения данных – вероятности ошибки, выносливости (числа циклов перезаписи) и времени хранения. Стандартным решением, позволяющим повысить надежность хранения данных в многоуровневой флеш-памяти, является введение помехоустойчивого кодирования. Эффективность введения помехоустойчивого кодирования в существенной степени определяется адекватностью модели, формализующей основные процессы, связанные с записью и чтением данных. В работе приводится описание основных искажений, сопровождающих процесс записи/считывания в NAND флеш-памяти, и явный вид плотностей распределения результирующего шума. В качестве аппроксимации полученных плотностей распределения результирующего шума рассматривается модель на основе композиции гауссова распределения и распределения Лапласа, достаточно адекватно отражающая плотности распределения результирующего шума при большом числе циклов перезаписи. Для этой модели проводится анализ помехоустойчивости каскадных кодовых конструкций с внешним кодом Рида-Соломона и внутренним многоуровневым кодом, состоящим из двоичных компонентных кодов. Выполненный анализ позволяет получить обменные соотношения между вероятностью ошибки, плотностью записи и числом циклов перезаписи. Полученные обменные соотношения показывают, что предложенные конструкции позволяют за счет очень незначительного снижения плотности записи обеспечить увеличение граничного значения числа циклов перезаписи (определяемого производителем) в 2–2.5 раза при сохранении требуемого значения вероятности ошибки на бит

Анализ эффективности каскадного кодирования для повышения выносливости многоуровневой NAND флеш-памяти

The increasing storage density of modern NAND flash memory chips, achieved both due to scaling down the cell size, and due to the increasing number of used cell states, leads to a decrease in data storage reliability, namely, error probability, endurance (number of P/E cycling) and retention time. Error correction codes are often used to improve the reliability of data storage in multilevel flash memory. The effectiveness of using error correction codes is largely determined by the model accuracy that exhibits the basic processes associated with writing and reading data. The paper describes the main sources of disturbances for a flash cell that affect the threshold voltage of the cell in NAND flash memory, and represents an explicit form of the threshold voltage distribution. As an approximation of the obtained threshold voltage distribution, a Normal-Laplace mixture model was shown to be a good fit in multilevel flash memories for a large number of rewriting cycles. For this model, a performance analysis of the concatenated coding scheme with an outer Reed-Solomon code and an inner multilevel code consisting of binary component codes is carried out. The performed analysis makes it possible to obtain tradeoffs between the error probability, storage density, and the number of P/E cycling. The resulting tradeoffs show that the considered concatenated coding schemes allow, due to a very slight decrease in the storage density, to increase the number of P/E cycling up to 2–2.5 times than their nominal endurance specification while maintaining the required value of the bit error probability.Повышение плотности записи в современных чипах NAND флеш-памяти, достигаемое как за счет уменьшающегося физического размера ячейки, так и благодаря возрастающему количеству используемых состояний ячейки, сопровождается снижением надежности хранения данных – вероятности ошибки, выносливости (числа циклов перезаписи) и времени хранения. Стандартным решением, позволяющим повысить надежность хранения данных в многоуровневой флеш-памяти, является введение помехоустойчивого кодирования. Эффективность введения помехоустойчивого кодирования в существенной степени определяется адекватностью модели, формализующей основные процессы, связанные с записью и чтением данных. В работе приводится описание основных искажений, сопровождающих процесс записи/считывания в NAND флеш-памяти, и явный вид плотностей распределения результирующего шума. В качестве аппроксимации полученных плотностей распределения результирующего шума рассматривается модель на основе композиции гауссова распределения и распределения Лапласа, достаточно адекватно отражающая плотности распределения результирующего шума при большом числе циклов перезаписи. Для этой модели проводится анализ помехоустойчивости каскадных кодовых конструкций с внешним кодом Рида-Соломона и внутренним многоуровневым кодом, состоящим из двоичных компонентных кодов. Выполненный анализ позволяет получить обменные соотношения между вероятностью ошибки, плотностью записи и числом циклов перезаписи. Полученные обменные соотношения показывают, что предложенные конструкции позволяют за счет очень незначительного снижения плотности записи обеспечить увеличение граничного значения числа циклов перезаписи (определяемого производителем) в 2–2.5 раза при сохранении требуемого значения вероятности ошибки на бит

Каскадное кодирование на основе многомерных решеток и кодов Рида — Соломона для многоуровневой флэш-памяти

The article considers concatenated coding scheme for multilevel flash memory. In this scheme the inner stage is a finite subset of a multidimensional lattice (lattice code) and the outer stage uses Reed–Solomon code. Performance analysis is done for a model characterizing the basic physical features of a flash memory cell with non-uniform target voltage levels and noise variance dependent on the recorded value (input-dependent additive Gaussian noise, ID-AGN). For this model we develop a new approach to evaluating the error probability for the inner code. This approach is based on one-dimensional numerical integration of product of the characteristic functions of random variables used in the decoding process. It is shown how the parameters of the concatenated coding scheme can be adapted to keep the required error probability when the retention period and/or number of program-erasure cycles increase.В работе рассмотрена каскадная схема кодирования для многоуровневой флэш-памяти, внутренняя ступень которой представляет собой конечное подмножество многомерной целочисленной решетки (lattice code), а в качестве внешней ступени используется код Рида — Соломона. Анализ помехоустойчивости предложенной каскадной схемы выполнен применительно к модели, отражающей основные физические особенности ячейки флэш-памяти с неравномерно расположенными целевыми уровнями напряжения в ячейке и дисперсией шума, зависящей от записанного значения (input-dependent additive Gaussian noise, ID-AGN). Для этой модели в работе развит новый подход к вычислению вероятности ошибки декодирования внутреннего кода на основе одномерного численного интегрирования произведений характеристических функций случайных величин, используемых декодером при вынесении решения. Показано, как при увеличении времени хранения и/или числа циклов перезаписи адаптировать параметры предложенной каскадной конструкции с тем, чтобы сохранить требуемый уровень вероятности ошибки

낸드플래시 메모리 오류정정을 위한 고성능 LDPC 복호방법 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 성원용.반도체 공정의 미세화에 따라 비트 에러율이 증가하는 낸드 플래시 메모리에서 고성능 에러 정정 방법은 필수적이다. Low-density parity-check (LDPC) 부호와 같은 연판정 에러 정정 부호는 뛰어난 에러 정정 성능을 보이지만, 높은 구현 복잡도로 인해 플래시 메모리 시스템에 적용되기 힘든 단점이 있다. 본 논문에서는 LDPC 부호의 효율적인 복호를 위해 고성능 메시지 전파 스케줄링 방법과 저 복잡도 복호 알고리즘을 제안한다. 특히 finite geometry (FG) LDPC 부호에 대한 효율적인 디코더 아키텍쳐를 제안하며, 구현된 디코더를 이용하여 낸드 플래시 메모리에 대해 연판정 복호시의 에너지 소모량에 대해 연구한다. 본 논문의 첫 번째 부분에서는 동적 스케줄링 (informed dynamic scheduling, IDS) 알고리즘의 성능향상 방법에 대해 연구한다. 이를 위해 우선 기존의 가장 빠른 수렴 속도를 보이는 IDS 알고리즘인 레지듀얼 신뢰 전파 (residual belief propagation, RBP) 알고리즘의 동작 특성을 분석하고, 이를 바탕으로 특정 노드에 메시지 갱신이 집중되는 것을 방지하여 RBP 알고리즘의 수렴속도를 증가시킨 improved RBP (iRBP) 알고리즘을 제안한다. 또한 iRBP의 뛰어난 수렴속도와 기존의 NS 알고리즘의 우수한 에러 정정 능력을 모두 갖춘 신드롬 기반의 혼합 스케줄링 (mixed scheduling) 방법을 제안한다. 끝으로 다양한 부호율의 LDPC 부호에 대한 모의실험을 통해 제안된 신드롬 기반의 혼합 스케줄링 방법이 본 논문에서 시험된 다른 모든 스케줄링 알고리즘의 성능을 능가함을 확인하였다. 논문의 두 번째 부분에서는 복호 실패시 많은 비트 에러를 발생시키는 a posteriori probability (APP) 알고리즘의 개선 방안에 방안을 제안한다. 또한 빠른 수렴속도와 우수한 에러 마루 (error-floor) 성능으로 데이터 저장장치에 적합한 FG-LDPC 부호에 대해 제안된 알고리즘이 적용된 하드웨어 아키텍처를 제안하였다. 제안된 아키텍처는 높은 노드 가중치를 가지는 FG-LDPC 부호에 적합하도록 쉬프트 레지스터 (shift registers)와 SRAM 기반의 혼합 구조를 채용하며, 높은 처리량을 얻기 위해 파이프라인된 병렬 아키텍처를 사용한다. 또한 메모리 사용량을 줄이기 위해 세 가지의 메모리 용량 감소 기법을 적용하며, 전력 소비를 줄이기 위해 두 가지의 저전력 기법을 제안한다. 본 제안된 아키텍처는 부호율 0.96의 (68254, 65536) Euclidean geometry LDPC 부호에 대해 0.13-um CMOS 공정에서 구현하였다. 마지막으로 본 논문에서는 연판정 복호가 적용된 낸드 플래시 메모리 시스템의 에너지 소모를 낮추는 방법에 대해 제안한다. 연판정 기반의 에러 정정 알고리즘은 높은 성능을 보이지만, 이는 플래시 메모리의 센싱 수와 에너지 소모를 증가 시키는 단점이 있다. 본 연구에서는 앞서 구현된 LDPC 디코더가 채용된 낸드 플래시 메모리 시스템의 에너지 소모를 분석하고, LDPC 디코더와 BCH 디코더 간의 칩 사이즈와 에너지 소모량을 비교하였다. 이와 더불어 본 논문에서는 LDPC 디코더를 이용한 센싱 정밀도 결정 방법을 제안한다. 본 연구를 통해 제안된 복호 및 스케줄링 알고리즘, VLSI 아키텍쳐, 그리고 읽기 정밀도 결정 방법을 통해 낸드 플래시 메모리 시스템의 에러 정정 성능을 극대화 하고 에너지 소모를 최소화 할 수 있다.High-performance error correction for NAND flash memory is greatly needed because the raw bit error rate increases as the semiconductor geometry shrinks for high density. Soft-decision error correction, such as low-density parity-check (LDPC) codes, offers high performance but their implementation complexity hinders wide adoption to consumer products. This dissertation proposes two high-performance message-passing schedules and a low-complexity decoding algorithm for LDPC codes. In particular, an efficient decoder architecture for finite geometry (FG) LDPC codes is proposed, and the energy consumption of soft-decision decoding for NAND flash memory is analyzed. The first part of this dissertation is devoted to improving the informed dynamic scheduling (IDS) algorithms. We analyze the behavior of the residual belief propagation (RBP), which is the fastest IDS algorithm, and develop an improved RBP (iRBP) by avoiding the concentration of message updates at a particular node. We also study the syndrome-based mixed scheduling of the iRBP and the node-wise scheduling (NS). The proposed mixed scheduling outperforms all other scheduling methods tested in this work. The next part of this dissertation is to develop a conditional variable node update scheme for the a posteriori probability (APP) algorithm. The developed algorithm is robust to decoding failures and can reduce the dynamic power consumption by lowering switching activities in the LDPC decoder. To implement the developed algorithm, we propose a memory-efficient pipelined parallel architecture for LDPC decoding. The architecture employs FG-LDPC codes that not only show fast convergence speed and good error-floor performance but also perform well with iterative decoding algorithms, which is especially suitable for data storage devices. We also developed a rate-0.96 (68254, 65536) Euclidean geometry LDPC code and implemented the proposed architecture in 0.13-um CMOS technology. This dissertation also covers low-energy error correction of NAND flash memory through soft-decision decoding. The soft-decision-based error correction algorithms show high performance, but they demand an increased number of flash memory sensing operations and consume more energy for memory access. We examine the energy consumption of a NAND flash memory system equipping an LDPC code-based soft-decision error correction circuit. The sum of energy consumed at NAND flash memory and the LDPC decoder is minimized. In addition, the chip size and energy consumption of the decoder were compared with those of two Bose-Chaudhuri-Hocquenghem (BCH) decoding circuits showing the comparable error performance and the throughput. We also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. This dissertation is intended to develop high-performance and low-power error correction circuits for NAND flash memory by studying improved decoding and scheduling algorithms, VLSI architecture, and a read precision selection method.1 Introduction 1 1.1 NAND Flash Memory 1 1.2 LDPC Codes 4 1.3 Outline of the Dissertation 6 2 LDPC Decoding and Scheduling Algorithms 8 2.1 Introduction 8 2.2 Decoding Algorithms for LDPC Codes 10 2.2.1 Belief Propagation Algorithm 10 2.2.2 Simplified Belief Propagation Algorithms 12 2.3 Message-Passing Schedules for Decoding of LDPC Codes 15 2.3.1 Static Schedules 15 2.3.2 Dynamic Schedules 17 3 Improved Dynamic Scheduling Algorithms for Decoding of LDPC Codes 22 3.1 Introduction 22 3.2 Improved Residual Belief Propagation Algorithm 23 3.3 Syndrome-Based Mixed Scheduling of iRBP and NS 26 3.4 Complexity Analysis and Simulation Results 28 3.4.1 Complexity Analysis 28 3.4.2 Simulation Results 29 3.5 Concluding Remarks 33 4 A Pipelined Parallel Architecture for Decoding of Finite-Geometry LDPC Codes 36 4.1 Introduction 36 4.2 Finite-Geometry LDPC Codes and Conditional Variable Node Update Algorithm 38 4.2.1 Finite-Geometry LDPC codes 38 4.2.2 Conditional Variable Node Update Algorithm for Fixed-Point Normalized APP-Based Algorithm 40 4.3 Decoder Architecture 46 4.3.1 Baseline Sequential Architecture 46 4.3.2 Pipelined-Parallel Architecture 54 4.3.3 Memory Capacity Reduction 57 4.4 Implementation Results 60 4.5 Concluding Remarks 64 5 Low-Energy Error Correction of NAND Flash Memory through Soft-Decision Decoding 66 5.1 Introduction 66 5.2 Energy Consumption of Read Operations in NAND Flash Memory 67 5.2.1 Voltage Sensing Scheme for Soft-Decision Data Output 67 5.2.2 LSB and MSB Concurrent Access Scheme for Low-Energy Soft-Decision Data Output 72 5.2.3 Energy Consumption of Read Operations in NAND Flash Memory 73 5.3 The Performance of Soft-Decision Error Correction over a NAND Flash Memory Channel 76 5.4 Hardware Performance of the (68254, 65536) LDPC Decoder 81 5.4.1 Energy Consumption of the LDPC Decoder 81 5.4.2 Performance Comparison of the LDPC Decoder and Two BCH Decoders 83 5.5 Low-Energy Error Correction Scheme for NAND Flash Memory 87 5.5.1 Optimum Precision for Low-Energy Decoding 87 5.5.2 Iteration Count-Based Precision Selection 90 5.6 Concluding Remarks 91 6 Conclusion 94 Bibliography 96 Abstract in Korean 110 감사의 글 112Docto

Energy-efficient memories for wireless sensor networks

Wireless sensor networks (WSNs) embed computation and sensing in the physical world, enabling an unprecedented spectrum of applications in several fields of daily life, such as environmental monitoring, cattle management, elderly care, and medicine to name a few. A WSN comprises sensor nodes, which represents a new class of networked embedded computer characterized by severe resource constraints. The design of a sensor node presents many challenges, as they are expected to be small, reliable, low cost, and low power, since they are powered from batteries or harvest energy from the surrounding environment. In a sensor node, the instantaneous power of the transceiver is usually several orders of magnitude higher than processing power. Nevertheless, if average power is considered in actual applications, the communication energy is only about two times higher than the processing energy. The scaling of CMOS technology provides higher performance at lower prices, enabling more refined distributed applications with augmented local processing. The increased complexity of applications demands for enlarged memory size, which in turn increases the power drain. This scenario becomes even worse as leakage power is becoming more and more important in small feature transistor sizes. In this work the energy consumption of a sensor node is characterized, and different memory architectures were investigated to be integrated in future wireless sensor networks, showing that SRAM memories with sleep state may benefit from low duty-cycle operating system. SRAM memory with power-manageable banks puts idle banks in sleep state to further reduce the leakage power, even when the system is active. Although it is a well known technique, the energy savings limits were not exhaustively stated, nor the inuence of the power management strategy adopted. We proposed a novel and detailed model of the energy saving for uniform banks with two power management schemes: a best-oracle policy and a simple greedy policy. Our model gives valuable insight into key factors (coming from the system and the workload) that are critical for reaching the maximum achievable energy saving. Thanks to our modeling, at design time a near optimum number of banks can be estimated to reach more aggressive energy savings. The memory content allocation problem was solved by an integer linear program formulation. In the framework of this thesis, experiments were carried out for two real wireless sensor network application (based on TinyOS and ContikiOS). Results showed energy reduction close to 80% for a partition overhead of 1% with a memory of ten banks for an application under high workload. Energy saving depends on the access patterns to memory and memory parameters (such as number of banks, partitioning overhead, energy reduction of the sleep state and the wake-up energy cost). The energy saving drops for low duty-cycles. However, a very significant reduction of energy can be achieved, for example, roughly 50% for a 3% duty-cycle operation using the above memory. Finally, our findings suggest that adopting an advanced power management must be carefully evaluated, since the best-oracle is only marginally better than a greedy policy.Las redes de sensores inalámbricas (RSI o WSN, por sus siglas en inglés) agregan computación y sensado al mundo fìsico, posibilitando un rango de aplicaciones sin precedentes en muchos campos de la vida cotidiana, como por ejemplo monitoreo ambiental, manejo de ganado, cuidado de personas adultas mayores y medicina, solo por mencionar algunas. Una RSI consta de nodos sensores, los cuales representan un nuevo tipo de computadora embebida en red, caracterizada por tener grandes restricciones de recursos. El diseño de un nodo sensor presenta muchos desafìos, ya que es necesario que sean, pequeños, confiables, de bajo costo y con muy bajo consumo de energía, ya que se alimentan de pilas o recolectan energía del medio. En un nodo sensor, la potencia instantánea del transceptor (radio) es usualmente algunos órdenes de magnitud mayor que la potencia de procesamiento. Sin embargo, la energía de comunicación es solamente dos veces mayor que la energía de procesamiento. Por otro lado, el escalado de la tecnología CMOS permite mayor performance a menores precios, posibilitando aplicaciones distribuídas más refinadas con más procesamiento local. El aumento de la complejidad de las aplicaciones requiere memorias de mayor tamaño, que a su vez aumenta el consumo de potencia. Este escenario empeora ya que las corrientes de fuga son cada vez más importantes en transistores de menor tamaño. En el presente trabajo de tesis se caracteriza el consumo de energía de un nodo sensor, y se investigan diferentes arquitecturas de memoria para ser integrado en las RSI futuras, mostrando como las memorias SRAM con un estado de sleep pueden ser convenientes en sistemas que operan con bajos ciclos de trabajo. Si además la memoria se divide en bancos que pueden ser controlados de manera independiente, se pueden poner los bancos inactivos en estado sleep, incluso cuando el sistema está activo. Aunque esta es una técnica conocida, los límites de ahorro de energía no habían sido exhaustivamente determinados, ni tampoco la influencia de la política de gestión de energía usado. Se propone un nuevo modelo detallado del ahorro de energía para bancos uniformes con dos políticas de gestión: best-oracle y greedy. Nuestro modelo proporciona información valiosa de los factores fundamentales (provenientes del sistema y la carga de trabajo) que son escenciales para alcanzar el máximo ahorro alcanzable. Gracias a nuestro modelado, en tiempo de diseño se puede estimar el número óptimo de bancos para lograr grandes ahorros de energía. El problema de asignación del código a los bancos fue resuelto usando programación lineal entera. En el contexto de esta tesis, se realizaron experimentos usando dos aplicaciones reales de redes de sensores inalámbricas (basadas en TinyOS y ContikiOS). Los resultados mostraron una reducción de energía cercano a 80% para un overhead de partición de 1% con una memoria de diez bancos para una aplicación con gran carga. El ahorro depende del patrón de acceso a memoria y los parámetros de la memoria (tales como cantidad de bancos, overhead de partición, reducción de energía del estado sleep y el costo energético de wake-up. El ahorro de energía decrece para ciclos de trabajo bajos. Sin embargo, igualmente se alcanzan ahorros de energía significativos, por ejemplo, aproximadamente 50% para ciclos de trabajo de 3% usando la memoria anterior. Finalmente, nuestros resultados sugieren que debe ser cuidadosamente evaluado el uso de políticas de gestón de energía avanzados, ya que la política best-oracle es sólo marginalmente mejor que la política greedy

낸드 플래시 메모리 신뢰도 향상을 위한 신호 처리 방법 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 성원용.The capacity of NAND flash memory has been continuously increased by aggressive technology scaling and multi-level cell (MLC) data coding. However, it becomes more challenging to maintain the current growth rate of the memory density mainly because of degraded signal quality of sub-20 nm NAND flash memory. This dissertation develops signal processing techniques to improve the signal reliability of MLC NAND flash memory. In the first part of this dissertation, we develop two threshold voltage distribution estimation algorithms to compensate the effect of program-erase (PE) cycling and charge loss in MLC NAND flash memory. The sensing directed estimation (SDE) utilizes the output of multi-level memory sensing to estimate the means and the variances of the threshold voltage distribution that is modeled as a Gaussian mixture. In order to reduce memory sensing overheads for the SDE algorithm, we develop a decision directed estimation (DDE) that uses error corrected bit patterns for more frequent updates of the model parameters. We also present a combined estimation scheme that employs both the SDE and the DDE approaches to minimize the number of memory sensing operations while maintaining the estimation accuracy. The effectiveness of the SDE and the DDE algorithms is evaluated by using both simulated and real NAND flash memory, and it is demonstrated that the proposed algorithms can estimate the statistical information of threshold voltage distribution accurately. The cell-to-cell interference (CCI) is one of the major sources of bit errors in sub-20 nm NAND flash memory and becomes more severe as the size of memory cell decreases. In the second part of this dissertation, we develop a CCI cancellation algorithm that is similar to interference cancellers employed in conventional communication systems. We first provide the experimental characterization of the CCI by measuring the coupling coefficients from actual NAND flash memory with a 26 nm process technology. Then, we present a CCI cancellation algorithm that consists of the coupling coefficient estimation and the CCI removal steps. To reduce the number of memory sensing operations, the optimal quantization schemes for the proposed CCI canceller are also studied. This dissertation also develops soft-information computation schemes in order to apply soft-decision error correction to NAND flash memory. The probability density function (PDF) of the CCI removed signal is quite different from that of the original threshold voltage, which can be modeled as a Gaussian mixture. Thus, computing soft-information, such as LLR (log likelihood ratio), with the CCI removed signal is not straightforward. We propose two soft-information computation schemes that combine CCI cancellation and soft-decision error correction. In the first approach, we derive a mathematical formulation for the PDF of the CCI removed signal and directly compute the LLR values by using it. In the second approach, CCI cancellation and soft-information computation are jointly conducted. Based on the intensive simulations, it is demonstrated that the reliability of NAND flash memory is significantly improved by applying the proposed signal processing algorithms as well as soft-decision error correction.1 Introduction 14 2 NAND Flash Memory Basics 19 2.1 Basics of NAND Flash Memory 19 2.1.1 NAND Flash Memory Structure 19 2.1.2 Multi-Page Programming 20 2.1.3 Cell-to-Cell Interference 22 2.1.4 Data Retention 23 2.2 Threshold Voltage Distribution of NAND Flash Memory and Signal Modeling 25 2.2.1 Threshold Voltage Distribution and Gaussian Approximation 25 2.2.2 Modeling of Threshold Voltage Signal 27 3 Threshold Voltage Distribution Estimation 31 3.1 Introduction 31 3.2 Sensing Directed Estimation of Threshold Voltage Distribution 33 3.2.1 Cost Function 34 3.2.2 Gradient Descent Method based Parameter Search 36 3.2.3 Levenberg-Marquardt Method based Parameter Search 38 3.2.4 Experimental Results 41 3.3 Decision Directed Estimation of Threshold Voltage Distribution 50 3.3.1 Basic Idea 51 3.3.2 Applying to Two-Bit MLC NAND Flash Memory 54 3.3.3 Combined Threshold Voltage Distribution Estimation 57 3.3.4 Error Analysis 58 3.3.5 Experimental Results 64 3.4 Concluding Remarks 70 4 Cell-to-Cell Interference Cancellation 71 4.1 Introduction 71 4.2 Direct Measurement of Coupling Coefficients 73 4.2.1 Measurement Procedure 74 4.2.2 Experimental Results 77 4.3 Least Squares Method based Coupling Coefficient Estimation 83 4.4 Multi-Level Memory Sensing Schemes for CCI Cancellation 87 4.5 Experimental Results 91 4.5.1 CCI Cancellation with Simulated NAND Flash Memory 91 4.5.2 CCI Cancellation with Real NAND Flash Memory 96 4.6 Concluding Remarks 97 5 Soft-Decision Error Correction in NAND Flash Memory 99 5.1 Introduction 99 5.2 Soft-Decision Error Correction without CCI Cancellation 101 5.3 Soft-Decision Error Correction with CCI Cancellation 104 5.3.1 Soft-Information Computation using PDF of CCI Removed Signal 104 5.3.2 Joint CCI Cancellation and Soft-Information Computation 110 5.3.3 Experimental Results 115 5.4 Concluding Remarks 118 6 Conclusion 120Docto