Systematic redundant residue number system codes: analytical upper bound and iterative decoding performance over AWGN and Rayleigh channels

The novel family of redundant residue number system (RRNS) codes is studied. RRNS codes constitute maximum–minimum distance block codes, exhibiting identical distance properties to Reed–Solomon codes. Binary to RRNS symbol-mapping methods are proposed, in order to implement both systematic and nonsystematic RRNS codes. Furthermore, the upper-bound performance of systematic RRNS codes is investigated, when maximum-likelihood (ML) soft decoding is invoked. The classic Chase algorithm achieving near-ML soft decoding is introduced for the first time for RRNS codes, in order to decrease the complexity of the ML soft decoding. Furthermore, the modified Chase algorithm is employed to accept soft inputs, as well as to provide soft outputs, assisting in the turbo decoding of RRNS codes by using the soft-input/soft-output Chase algorithm. Index Terms—Redundant residue number system (RRNS), residue number system (RNS), turbo detection

EVALUASI METODE LOAD BALANCING Dan FAULT TOLERANCE PADA SISTEM DATABASE SERVER APLIKASI CHAT

Abstract The development of social network applications has growth so fast with various applications supported by smart tools as multiplatform to used it. Several applications that used by user are the chat and media social app. However, there is problem is the number of users accessing the chat service is large. This condition makes communication into database server can be stop and loss of data. It is caused by excessive load received by a single server database. Therefore, this study designs a database server to solve a lot of users of communication server and storage capacity into database server more than one. This is important because to increase availibiliy of services for each users request. This study used a method of distribution of communications service request for each database  server. Distribution of communication service request used a load balancing method and HAPRoxy with scheduling method. There are two algorithms in scheduling method are round robin and least connection algorithm. Both of algorithms were evaluated. compared, and used in database server more than one. The result shown average of least connection algorithm has value of response time 32.421 ms is smaller than round robin algorithm 35.813 ms. While on the throughput, least algorithm has big value 211.267 Kb/s than round robin algorithm has value 210.298 Kb/s. The result shown the number of packet least connection algorithm are big and better than round robin algortihm with load balancing implementation for distribution of server communication on database server more than one able to solve a lot of services communication. Keywords: load balancing, database server chat, least connection, round robin, response time, throughpu

Architectures and implementations for the Polynomial Ring Engine over small residue rings

This work considers VLSI implementations for the recently introduced Polynomial Ring Engine (PRE) using small residue rings. To allow for a comprehensive approach to the implementation of the PRE mappings for DSP algorithms, this dissertation introduces novel techniques ranging from system level architectures to transistor level considerations. The Polynomial Ring Engine combines both classical residue mappings and new polynomial mappings. This dissertation develops a systematic approach for generating pipelined systolic/ semi-systolic structures for the PRE mappings. An example architecture is constructed and simulated to illustrate the properties of the new architectures. To simultaneously achieve large computational dynamic range and high throughput rate the basic building blocks of the PRE architecture use transistor size profiling. Transistor sizing software is developed for profiling the Switching Tree dynamic logic used to build the basic modulo blocks. The software handles complex nFET structures using a simple iterative algorithm. Issues such as convergence of the iterative technique and validity of the sizing formulae have been treated with an appropriate mathematical analysis. As an illustration of the use of PRE architectures for modem DSP computational problems, a Wavelet Transform for HDTV image compression is implemented. An interesting use is made of the PRE technique of using polynomial indeterminates as \u27placeholders\u27 for components of the processed data. In this case we use an indeterminate to symbolically handle the irrational number [square root of 3] of the Daubechie mother wavelet for N = 4. Finally, a multi-level fault tolerant PRE architecture is developed by combining the classical redundant residue approach and the circuit parity check approach. The proposed architecture uses syndromes to correct faulty residue channels and an embedded parity check to correct faulty computational channels. The architecture offers superior fault detection and correction with online data interruption

Calcul sur architecture non fiable

Although materials could be fabricated as error-free theoretically with a huge cost for worst-case design methodologies, the circuit is still susceptible to transient faults by the effects of radiation, temperature sensitivity, and etc. On the contrary, an error-resilient design enables the manufacturing process to be relieved from the variability issue so as to save material cost. Since variability and transient upsets are worsening as emerging fabrication process and size shrink are tending intense, the requirement of robust design is imminent. This thesis addresses the issue of designing on unreliable circuit. The main contributions are fourfold. Firstly a fast error-correction and low cost redundancy fault-tolerant method is presented. Moreover, we introduce judicious two-dimensional criteria to estimate the reliability and the hardware efficiency of a circuit. A general-purpose model offers low-redundancy error-resilience for contemporary logic systems as well as future nanoeletronic architectures. At last, a decoder against internal transient faults is designed in this work.En théorie, les circuits électroniques conçus selon la méthode du pire-cas sont supposés garantir un fonctionnement sans erreur pourun coût d’implémentation élevé. Dans la pratique les circuits restent sujets aux erreurs transitoires du fait de leur sensibilité aux aléastels que la radiation et la température. En revanche, une conception prenant en compte la tolérance aux fautes permet de faire face à detels aléas comme la variabilité du processus de fabrication. De plus, les erreurs transitoires et la variabilité de fabrication s’intensifientavec l’émergence de nouveaux processus de fabrication et des circuits de dimension de plus en plus réduite. La demande d’une conceptionintégrant la tolérance aux fautes devient désormais primordiale. La présente thèse a pour objectif de cerner la problématique de laconception de circuits sur des puces peu fiables et apporte des contributions suivant quatre aspects. Dans un premier temps, nous proposonsune méthode de tolérance aux fautes, basée sur la correction d’erreurs et la redondance à faible coût. Puis, nous présentonsun critère bidimensionnel judicieux permettant d’évaluer la fiabilité et l’efficacité matérielle de circuits. Nous proposons ensuite un modèleuniversel qui apporte une tolérance avec fautes à redondance faible pour les systèmes logiques d’aujourd’hui et les architecturesnanoélectroniques de demain. Enfin, nous découvrons un décodeur tolérant aux fautes transitoires internes

Reliable & Efficient Data Centric Storage for Data Management in Wireless Sensor Networks

Wireless Sensor Networks (WSNs) have become a mature technology aimed at performing environmental monitoring and data collection. Nonetheless, harnessing the power of a WSN presents a number of research challenges. WSN application developers have to deal both with the business logic of the application and with WSN's issues, such as those related to networking (routing), storage, and transport. A middleware can cope with this emerging complexity, and can provide the necessary abstractions for the definition, creation and maintenance of applications. The final goal of most WSN applications is to gather data from the environment, and to transport such data to the user applications, that usually resides outside the WSN. Techniques for data collection can be based on external storage, local storage and in-network storage. External storage sends data to the sink (a centralized data collector that provides data to the users through other networks) as soon as they are collected. This paradigm implies the continuous presence of a sink in the WSN, and data can hardly be pre-processed before sent to the sink. Moreover, these transport mechanisms create an hotspot on the sensors around the sink. Local storage stores data on a set of sensors that depends on the identity of the sensor collecting them, and implies that requests for data must be broadcast to all the sensors, since the sink can hardly know in advance the identity of the sensors that collected the data the sink is interested in. In-network storage and in particular Data Centric Storage (DCS) stores data on a set of sensors that depend on a meta-datum describing the data. DCS is a paradigm that is promising for Data Management in WSNs, since it addresses the problem of scalability (DCS employs unicast communications to manage WSNs), allows in-network data preprocessing and can mitigate hot-spots insurgence. This thesis studies the use of DCS for Data Management in middleware for WSNs. Since WSNs can feature different paradigms for data routing (geographical routing and more traditional tree routing), this thesis introduces two different DCS protocols for these two different kinds of WNSs. Q-NiGHT is based on geographical routing and it can manage the quantity of resources that are assigned to the storage of different meta-data, and implements a load balance for the data storage over the sensors in the WSN. Z-DaSt is built on top of ZigBee networks, and exploits the standard ZigBee mechanisms to harness the power of ZigBee routing protocol and network formation mechanisms. Dependability is another issue that was subject to research work. Most current approaches employ replication as the mean to ensure data availability. A possible enhancement is the use of erasure coding to improve the persistence of data while saving on memory usage on the sensors. Finally, erasure coding was applied also to gossiping algorithms, to realize an efficient data management. The technique is compared to the state-of-the-art to identify the benefits it can provide to data collection algorithms and to data availability techniques

Approche arithmétique RNS de la cryptographie asymétrique

This thesis is at the crossroads between cryptography and computer arithmetic. It deals with enhancement of cryptographic primitives with regard to computation acceleration and protection against fault injections through the use of residue number systems (RNS) and their associated arithmetic. So as to contribute to secure the modular multiplication, which is a core operation for many asymmetric cryptographic primitives, a new modular reduction algorithm supplied with fault detection capability is presented. A formal proof guarantees that faults affecting one or more residues during a modular reduction are well detected. Furthermore, this approach is generalized to an arithmetic dedicated to non-prime finite fields Fps . Afterwards, RNS are used in lattice-based cryptography area. The aim is to exploit acceleration properties enabled by RNS, as it is widely done for finite field arithmetic. As first result, a new version of Babai’s round-off algorithm based on hybrid RNS-MRS representation is presented. Then, a new and specific acceleration technique enables to create a full RNS algorithm computing a close lattice vector.Cette thèse se situe à l'intersection de la cryptographie et de l'arithmétique des ordinateurs. Elle traite de l'amélioration de primitives cryptographiques asymétriques en termes d'accélération des calculs et de protection face aux attaques par fautes par le biais particulier de l'utilisation des systèmes de représentation des nombres par les restes (RNS). Afin de contribuer à la sécurisation de la multiplication modulaire, opération centrale en cryptographie asymétrique, un nouvel algorithme de réduction modulaire doté d'une capacité de détection de faute est présenté. Une preuve formelle garantit la détection des fautes sur un ou plusieurs résidus pouvant apparaître au cours d'une réduction. De plus, le principe de cet algorithme est généralisé au cas d'une arithmétique dans un corps fini non premier. Ensuite, les RNS sont exploités dans le domaine de la cryptographie sur les réseaux euclidiens. L'objectif est d'importer dans ce domaine certains avantages des systèmes de représentation par les restes dont l'intérêt a déjà été montré pour une arithmétique sur GF(p) notamment. Le premier résultat obtenu est une version en représentation hybride RNS-MRS de l'algorithme du « round-off » de Babai. Puis une technique d'accélération est introduite, permettant d'aboutir dans certains cas à un algorithme entièrement RNS pour le calcul d'un vecteur proche