Asynchronous Circuit Stacking for Simplified Power Management

As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the ICs operate at. By stacking multiple MTNCL circuits between power and ground, supplying a multiple of VDD to the entire stack and incorporating simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm SOI process for demonstrating the feasibility and analyzing the advantages of the proposed MTNCL stacking architecture

Curved-crease origami face shields for infection control

The COVID-19 pandemic has created enormous global demand for personal protective equipment (PPE). Face shields are an important component of PPE for front-line workers in the context of the COVID-19 pandemic, providing protection of the face from splashes and sprays of virus-containing fluids. Existing face shield designs and manufacturing procedures may not allow for production and distribution of face shields in sufficient volume to meet global demand, particularly in Low and Middle-Income countries. This paper presents a simple, fast, and cost-effective curved-crease origami technique for transforming flat sheets of flexible plastic material into face shields for infection control. It is further shown that the design could be produced using a variety of manufacturing methods, ranging from manual techniques to high-volume die-cutting and creasing. This demonstrates the potential for the design to be applied in a variety of contexts depending on available materials, manufacturing capabilities and labour. An easily implemented and flexible physical-digital parametric design methodology for rapidly exploring and refining variations on the design is presented, potentially allowing others to adapt the design to accommodate a wide range of ergonomic and protection requirements

40.4fJ/bit/mm Low-Swing On-Chip Signaling with Self-Resetting Logic Repeaters Embedded within a Mesh NoC in 45nm SOI CMOS

Mesh NoCs are the most widely-used fabric in high-performance many-core chips today. They are, however, becoming increasingly power-constrained with the higher on-chip bandwidth requirements of high-performance SoCs. In particular, the physical datapath of a mesh NoC consumes significant energy. Low-swing signaling circuit techniques can substantially reduce the NoC datapath energy, but existing low-swing circuits involve huge area footprints, unreliable signaling or considerable system overheads such as an additional supply voltage, so embedding them into a mesh datapath is not attractive. In this paper, we propose a novel low-swing signaling circuit, a self-resetting logic repeater, to meet these design challenges. The SRLR enables single-ended low-swing pulses to be asynchronously repeated, and hence, consumes less energy than differential, clocked low-swing signaling. To mitigate global process variations while delivering high energy efficiency, three circuit techniques are incorporated. Fabricated in 45nm SOI CMOS, our 10mm SRLR-based low-swing datapath achieves 6.83Gb/s/µm bandwidth density with 40.4fJ/bit/mm energy at 4.1Gb/s data rate at 0.8V.United States. Defense Advanced Research Projects Agency. The Ubiquitous High-Performance Computing Progra

Statistical Approach for Yield Optimization for Minimum Energy Operation in Subthreshold Circuits Considering Variability Issues

The supply voltage (V-dd) and threshold voltage (V-th) are two significant design variables that directly impact the performance and power consumption of circuits. The scaling of these voltages has become a popular option to satisfy performance and low power requirements. Subthreshold operation is a compelling approach for energy-constrained applications where processor speed is less important. However, subthreshold designs show dramatically increased sensitivity to process variations due to the exponential relationship of subthreshold drive current with V-th variation and drastically growing leakage power. If there is uncertainty in the value of the threshold or supply voltage, the power advantages of this very low-voltage operation diminishes. This paper presents a statistical methodology for choosing the optimum V-dd and V-th under manufacturing uncertainties and different operating conditions to minimize energy for a given frequency in subthreshold operation while ensuring yield maximality. Unlike the traditional energy optimization, to find the optimal values for the voltages, we have considered the following factors to make the optimization technique more acceptable: the application-dependent design constraints, variations in the design variables due to manufacturing uncertainty, device sizing, activity factor of the circuit, and power reduction techniques. To maximize the yield, a two-level optimization is employed. First, the design metric is carefully chosen and deterministically optimized to the optimum point in the feasible region. At the second level, a tolerance box is moved over the design space to find the best location in order to maximize the yield. The feasible region, which is application dependent, is constrained by the minimum performance and the maximum ratio of leakage to total power in the V-dd-V-th plane. The center of the tolerance box provides the nominal design values for V-dd and V-th such that the design has a maximum immunity to the variations and maximizes the yield. The yield is estimated directly using the joint cumulative distribution function over the tolerance box requiring no numerical integration and saving considerable computational complexity for multidimensional problems. The optimal designs, verified by Monte Carlo and SPECTRE simulations, demonstrate significant increase in yield. By using this methodology, yield is found to be strongly dependent on the design metrics, circuit switching activity, transistor sizing, and the given constraints

Stream Processor Development using Multi-Threshold NULL Convention Logic Asynchronous Design Methodology

Decreasing transistor feature size has led to an increase in the number of transistors in integrated circuits (IC), allowing for the implementation of more complex logic. However, such logic also requires more complex clock tree synthesis (CTS) to avoid timing violations as the clock must reach many more gates over larger areas. Thus, timing analysis requires significantly more computing power and designer involvement than in the past. For these reasons, IC designers have been pushed to nix conventional synchronous (SYNC) architecture and explore novel methodologies such as asynchronous, self-timed architecture. This dissertation evaluates the nominal active energy, voltage-scaled active energy, and leakage power dissipation across two cores of a stream processor: Smoothing Filter (SF) and Histogram Equalization (HEQ). Both cores were implemented in Multi-Threshold NULL Convention Logic (MTNCL) and clock-gated synchronous methodologies using a gate-level netlist to avoid any architectural discrepancies while guaranteeing impartial comparisons. MTNCL designs consumed more active energy than their synchronous counterparts due to the dual-rail encoding system; however, high-threshold-voltage (High-Vt) transistors used in MTNCL threshold gates reduced leakage power dissipation by up to 227%. During voltage-scaling simulations, MTNCL circuits showed a high level of robustness as the output results were logically valid across all voltage sweeps without any additional circuitry. SYNC circuits, however, needed extra logic, such as a DVS controller, to adjust the circuit’s speed when VDD changed. Although SYNC circuits still consumed less average energy, MTNCL circuit power gains accelerated when switching to lower voltage domains

Stream Processor Development using Multi-Threshold NULL Convention Logic Asynchronous Design Methodology

Decreasing transistor feature size has led to an increase in the number of transistors in integrated circuits (IC), allowing for the implementation of more complex logic. However, such logic also requires more complex clock tree synthesis (CTS) to avoid timing violations as the clock must reach many more gates over larger areas. Thus, timing analysis requires significantly more computing power and designer involvement than in the past. For these reasons, IC designers have been pushed to nix conventional synchronous (SYNC) architecture and explore novel methodologies such as asynchronous, self-timed architecture. This dissertation evaluates the nominal active energy, voltage-scaled active energy, and leakage power dissipation across two cores of a stream processor: Smoothing Filter (SF) and Histogram Equalization (HEQ). Both cores were implemented in Multi-Threshold NULL Convention Logic (MTNCL) and clock-gated synchronous methodologies using a gate-level netlist to avoid any architectural discrepancies while guaranteeing impartial comparisons. MTNCL designs consumed more active energy than their synchronous counterparts due to the dual-rail encoding system; however, high-threshold-voltage (High-Vt) transistors used in MTNCL threshold gates reduced leakage power dissipation by up to 227%. During voltage-scaling simulations, MTNCL circuits showed a high level of robustness as the output results were logically valid across all voltage sweeps without any additional circuitry. SYNC circuits, however, needed extra logic, such as a DVS controller, to adjust the circuit’s speed when VDD changed. Although SYNC circuits still consumed less average energy, MTNCL circuit power gains accelerated when switching to lower voltage domains

Current Feedback-Based High Load Current Low Drop-Out Voltage Regulator in 65-nm CMOS Technology

The motivation for this paper was to design a current feedback-based high load current, low drop-out (LDO) voltage regulator. A bandgap voltage reference (BGR) was also designed in conjunction with the LDO to simulate realistic environments. The schematic was designed with Cadence Virtuoso Schematic XL, using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS library, used for Internet of Things (IoT) System on Chip (SoC) applications. The proposed capacitor-less LDO with BGR provided an average temperature coefficient (TC) of 13.34 ppm/℃ within the range of -40 to 125 ℃. This was in accordance with military standards to gain a higher stability and power supply rejection ratio (PSRR). The proposed capacitor-less LDO also achieved a 200 mA load current with an error percentage of 0.246% and a -21.47 dB PSRR at 100 KHz with a current based structure. This thesis concluded with the application of capacitor-less LDO in medical IoT devices, followed by the future of medical device development