In-memory photonic dot-product engine with electrically programmable weight banks

Electronically reprogrammable photonic circuits based on phase-change chalcogenides present an avenue to resolve the von-Neumann bottleneck; however, implementation of such hybrid photonic–electronic processing has not achieved computational success. Here, we achieve this milestone by demonstrating an in-memory photonic–electronic dot-product engine, one that decouples electronic programming of phase-change materials (PCMs) and photonic computation. Specifically, we develop non-volatile electronically reprogrammable PCM memory cells with a record-high 4-bit weight encoding, the lowest energy consumption per unit modulation depth (1.7 nJ/dB) for Erase operation (crystallization), and a high switching contrast (158.5%) using non-resonant silicon-on-insulator waveguide microheater devices. This enables us to perform parallel multiplications for image processing with a superior contrast-to-noise ratio (≥87.36) that leads to an enhanced computing accuracy (standard deviation σ ≤ 0.007). An in-memory hybrid computing system is developed in hardware for convolutional processing for recognizing images from the MNIST database with inferencing accuracies of 86% and 87%

Développement et optimisation au niveau des matériaux des mémoires résistives à changement de valence pour le calcul-en-mémoire

Le développement des technologies de mémoires résistives non-volatiles a permis d’explorer de nouvelles approches de calcul plus performantes que celles basées sur l’architecture conventionnelle de von Neumann. Notamment, l’approche de calcul-en-mémoire propose une solution à l’étranglement de von Neumann en poussant l’idée de concevoir une architecture où il n’y a pas de séparation physique entre le processeur et la mémoire. Cette approche repose sur les propriétés uniques des mémoires résistives (mémristors) lorsqu’elles sont agencées en réseaux crossbar, où les fonctions de sommation et de multiplication s’implémentent de manière naturelle. De plus, la compatibilité de ces mémoires pour une intégration avec les technologies CMOS conventionnelles offre des capacités agressives de miniaturisation et d’efficacité énergétique. Pour répondre aux exigences de cette intégration, cette thèse a porté d’abord sur le développement du procédé de dépôt du matériau à commutation de résistance (TiO2). L’influence de la concentration de défauts sur les propriétés optiques, structurales et sur la composition chimique du TiO2 a été évaluée. Par la suite, le matériau à commutation de résistance développé a été utilisé pour la fabrication de mémristors de structure TiN/Al2O3/TiO2-x/Ti/TiN/Al. Le procédé de fabrication utilisé est compatible CMOS et s’est basé sur le procédé damascène pour réduire la rugosité de surface des électrodes afin de minimiser la variabilité entre composants (device-to-device variability). Les caractéristiques électriques des mémristors ont été évaluées en quasi-statique ainsi qu’en utilisant des courtes impulsions de tension pour reproduire les conditions réelles d’opération. Les propriétés de commutation résistive analogique ainsi que les fonctions synaptiques de potentialisation et de dépression à long terme ont été démontré. Les mémristors fabriqués peuvent stocker jusqu’à 3 bits avec une stabilité temporelle satisfaisante. Pour réduire les tensions de forming de nos composants, des stratégies combinant la modulation de la concentration de défauts et l’épaisseur du matériau actif ainsi qu’une étape de traitement thermique post-dépôt ont été étudiées. Cette thèse a permis de mettre en oeuvre un procédé de dépôt du matériau à commutation de résistance, d’évaluer les caractéristiques électriques des mémristors et leur potentiel à implémenter les fonctions synaptiques, ainsi que d’explorer des stratégies pertinentes qui peuvent minimiser l’influence des tensions de forming sur l’opération optimale des réseau crossbar

Parallel convolution processing using an integrated photonic tensor core

With the proliferation of ultra-high-speed mobile networks and internet-connected devices, along with the rise of artificial intelligence, the world is generating exponentially increasing amounts of data - data that needs to be processed in a fast, efficient and smart way. These developments are pushing the limits of existing computing paradigms, and highly parallelized, fast and scalable hardware concepts are becoming progressively more important. Here, we demonstrate a computational specific integrated photonic tensor core - the optical analog of an ASIC-capable of operating at Tera-Multiply-Accumulate per second (TMAC/s) speeds. The photonic core achieves parallelized photonic in-memory computing using phase-change memory arrays and photonic chip-based optical frequency combs (soliton microcombs). The computation is reduced to measuring the optical transmission of reconfigurable and non-resonant passive components and can operate at a bandwidth exceeding 14 GHz, limited only by the speed of the modulators and photodetectors. Given recent advances in hybrid integration of soliton microcombs at microwave line rates, ultra-low loss silicon nitride waveguides, and high speed on-chip detectors and modulators, our approach provides a path towards full CMOS wafer-scale integration of the photonic tensor core. While we focus on convolution processing, more generally our results indicate the major potential of integrated photonics for parallel, fast, and efficient computational hardware in demanding AI applications such as autonomous driving, live video processing, and next generation cloud computing services

Filament‐Free Bulk Resistive Memory Enables Deterministic Analogue Switching

Digital computing is nearing its physical limits as computing needs and energy consumption rapidly increase. Analogue‐memory‐based neuromorphic computing can be orders of magnitude more energy efficient at data‐intensive tasks like deep neural networks, but has been limited by the inaccurate and unpredictable switching of analogue resistive memory. Filamentary resistive random access memory (RRAM) suffers from stochastic switching due to the random kinetic motion of discrete defects in the nanometer‐sized filament. In this work, this stochasticity is overcome by incorporating a solid electrolyte interlayer, in this case, yttria‐stabilized zirconia (YSZ), toward eliminating filaments. Filament‐free, bulk‐RRAM cells instead store analogue states using the bulk point defect concentration, yielding predictable switching because the statistical ensemble behavior of oxygen vacancy defects is deterministic even when individual defects are stochastic. Both experiments and modeling show bulk‐RRAM devices using TiO2‐X switching layers and YSZ electrolytes yield deterministic and linear analogue switching for efficient inference and training. Bulk‐RRAM solves many outstanding issues with memristor unpredictability that have inhibited commercialization, and can, therefore, enable unprecedented new applications for energy‐efficient neuromorphic computing. Beyond RRAM, this work shows how harnessing bulk point defects in ionic materials can be used to engineer deterministic nanoelectronic materials and devices.A resistive memory cell based on the electrochemical migration of oxygen vacancies for in‐memory neuromorphic computing is presented. By using the average statistical behavior of all oxygen vacancies to store analogue information states, this cell overcomes the stochastic and unpredictable switching plaguing filament‐forming memristors, and instead achieves linear, predictable, and deterministic switching.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/163547/3/adma202003984_am.pdfhttp://deepblue.lib.umich.edu/bitstream/2027.42/163547/2/adma202003984-sup-0001-SuppMat.pdfhttp://deepblue.lib.umich.edu/bitstream/2027.42/163547/1/adma202003984.pd

More is Less, Less is More: Molecular-Scale Photonic NoC Power Topologies

Abstract Molecular-scale Network-on-Chip (mNoC) crossbars use quantum dot LEDs as an on-chip light source, and chromophores to provide optical signal filtering for receivers. An mNoC reduces power consumption or enables scaling to larger crossbars for a reduced energy budget compared to current nanophotonic NoC crossbars. Since communication latency is reduced by using a high-radix crossbar, minimizing power consumption becomes a primary design target. Conventional Single Writer Multiple Reader (SWMR) photonic crossbar designs broadcast all packets, and incur the commensurate required power, even if only two nodes are communicating. This paper introduces power topologies, enabled by unique capabilities of mNoC technology, to reduce overall interconnect power consumption. A power topology corresponds to the logical connectivity provided by a given power mode. Broadcast is one power mode and it consumes the maximum power. Additional power modes consume less power but allow a source to communicate with only a statically defined, potentially non-contiguous, subset of nodes. Overall interconnect power is reduced if the more frequently communicating nodes use modes that consume less power, while less frequently communicating nodes use modes that consume more power. We also investigate thread mapping techniques to fully exploit power topologies. We explore various mNoC power topologies with one, two and four power modes for a radix-256 SWMR mNoC crossbar. Our results show that the combination of power topologies and intelligent thread mapping can reduce total mNoC power by up Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. to 51% on average for a set of 12 SPLASH benchmarks. Furthermore performance is 10% better than conventional resonator-based photonic NoCs and energy is reduced by 72%

Applications of Multi-Terminal Memristive Devices: A Review

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devices, whose practical realization has been demonstrated within a broad range of different technologies. For electron devices, the memristive functionality can be generally attributed to a state modification, whose dynamics can be engineered to target a specific application. In this review paper, we show examples of two-terminal Resistive RAMs (ReRAM) for standalone memory and Field Programmable Gate Arrays (FPGA) applications. Moreover, a Generic Memory Structure (GMS) utilizing two ReRAMs for 3D-FPGA is discussed. In addition, we show that trap charging dynamics can explain some of the memristive effects previously reported for Schottky-barrier field-effect Si nanowire transistors (SB SiNW FETs). Moreover, the SB SiNW FETs do show additional memristive functionality due to trap charging at the metal/semiconductor surface. The combination of these two memristive effects into multi-terminal MOSFET devices gives rise to new opportunities for both memory and logic applications as well as new sensors based on the physical mechanism that originate memristance. Finally, the multi-terminal memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid CMOS co-fabrication with a CMOS-compatible process