370 research outputs found
A Robust Self-calibrating Transmission Scheme for On-Chip Networks
Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. We examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity-in spite of the decreased signal to noise ratio-by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements
Limits on Fundamental Limits to Computation
An indispensable part of our lives, computing has also become essential to
industries and governments. Steady improvements in computer hardware have been
supported by periodic doubling of transistor densities in integrated circuits
over the last fifty years. Such Moore scaling now requires increasingly heroic
efforts, stimulating research in alternative hardware and stirring controversy.
To help evaluate emerging technologies and enrich our understanding of
integrated-circuit scaling, we review fundamental limits to computation: in
manufacturing, energy, physical space, design and verification effort, and
algorithms. To outline what is achievable in principle and in practice, we
recall how some limits were circumvented, compare loose and tight limits. We
also point out that engineering difficulties encountered by emerging
technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl
State Dependent Statistical Timing Model for Voltage Scaled Circuits
This paper presents a novel statistical state-dependent timing model for
voltage over scaled (VoS) logic circuits that accurately and rapidly finds the
timing distribution of output bits. Using this model erroneous VoS circuits can
be represented as error-free circuits combined with an error-injector. A case
study of a two point DFT unit employing the proposed model is presented and
compared to HSPICE circuit simulation. Results show an accurate match, with
significant speedup gains
Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors
The progress of microelectronics making possible higher integration densities, and a considerable development of on-board systems are currently undergoing, this growth comes up against a limiting factor of power dissipation. Higher power dissipation will cause an immediate spread of generated heat which causes thermal problems. Consequently, the system's total consumed energy will increase as the system temperature increase.
High temperatures in microprocessors and large thermal energy of computer systems produce huge problems of system confidence, performance, and cooling expenses. Power consumed by processors are mainly due to the increase in number of cores and the clock frequency, which is dissipated in the form of heat and causes thermal challenges for chip designers. As the microprocessor’s performance has increased remarkably in
Nano-meter technology, power dissipation is becoming non-negligible. To solve this problem, this article addresses power dissipation reduction issues for high performance processors using multi-objective Pareto front (PF), and particle swarm optimization (PSO) algorithms to achieve power dissipation as a prior computation that reduces the real delay of a target microprocessor unit. Simulation is verified the conceptual fundamentals and optimization of joint body and supply voltages (Vth-VDD) which showing satisfactory findings
Closed-form crosstalk noise metrics for physical design applications
ABSTRACT In this paper we present efficient closed-form formulas to estimate capacitive coupling-induced crosstalk noise for distributed RC coupling trees. The efficiency of our approach stems from the fact that only the five basic operations are used in the expressions: addition ( ), subtraction ( ), multiplication ( ), division ( ) and square root ( ). The formulas do not require exponent computation or numerical iterations. We have developed closed-form expressions for the peak crosstalk noise amplitude, the peak noise occurring time and the width of the noise waveform. Our approximations are conservative and yet achieve acceptable accuracy. The formulas are simple enough to be used in the inner loops of performance optimization algorithms or as cost functions to guide routers. They capture the influence of coupling direction (near-end and far-end coupling) and coupling location (near-driver and nearreceiver)
Information-Theoretic Modeling and Analysis of Stochastic Behaviors in Quantum-Dot Cellular Automata
ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN
As the MOSFET dimensions scale down towards nanoscale level, the reliability of
circuits based on these devices decreases. Hence, designing reliable systems using
these nano-devices is becoming challenging. Therefore, a mechanism has to be
devised that can make the nanoscale systems perform reliably using unreliable circuit
components. The solution is fault-tolerant circuit design. Markov Random Field
(MRF) is an effective approach that achieves fault-tolerance in integrated circuit
design. The previous research on this technique suffers from limitations at the design,
simulation and implementation levels. As improvements, the MRF fault-tolerance
rules have been validated for a practical circuit example. The simulation framework is
extended from thermal to a combination of thermal and random telegraph signal
(RTS) noise sources to provide a more rigorous noise environment for the simulation
of circuits build on nanoscale technologies. Moreover, an architecture-level
improvement has been proposed in the design of previous MRF gates. The redesigned
MRF is termed as Improved-MRF.
The CMOS, MRF and Improved-MRF designs were simulated under application
of highly noisy inputs. On the basis of simulations conducted for several test circuits,
it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10
times more noise-tolerant than the CMOS alternatives. The number of transistors, on
the other hand increased from a factor of 9 to 15 from MRF to Improved-MRF
respectively (as compared to the CMOS). Therefore, in order to provide a trade-off
between reliability and the area overhead required for obtaining a fault-tolerant
circuit, a novel parameter called as ‘Reliable Area Index’ (RAI) is introduced in this
research work. The value of RAI exceeds around 1.3 and 40 times for MRF and
Improved-MRF respectively as compared to CMOS design which makes Improved-
MRF to be still 30 times more efficient circuit design than MRF in terms of
maintaining a suitable trade-off between reliability and area-consumption of the
circuit
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