Discrimination of surface and volume states in fully depleted field-effect devices on thick insulator substrates

The behavior of electronic devices fabricated on thin, lightly doped semiconductor layers can be significantly influenced by very low levels of non-ideal charge states. Such devices typically operate in a fully depleted mode, and can exhibit significantly different electrical properties and characteristics than their bulk material counterparts. Traditional interpretation of device characteristics may identify the existence of such non-idealities, but fail to ascertain if the origin is from within the semiconductor layer or associated with the interfaces to adjacent dielectric materials. This leads to ambiguity in how to rectify the behavior and improve device performance. Characterizing non-idealities through electrical means requires adaptations in both measurement techniques and data interpretation. Some of these adaptations have been applied in material systems like silicon-on-insulator (SOI), however in systems where the semiconductor film becomes increasingly isolated on very thick insulators (i.e., glass), the device physics of operation presents new challenges. Overcoming the obstacles in interpretation can directly aid the technology development of thin semiconductor films on thick insulator substrates. The investigation is initiated by isolating the interface of crystalline silicon bonded to a thick boro-aluminosilicate glass insulator. The interface is studied through traditional bulk capacitance-voltage (C-V) methods, and the electrical fragility of the interface is exposed. This reveals the necessity to discriminate between interface states and bulk defect states. To study methods of discrimination, the physics of field-effect devices fabricated on isolated semiconducting films is explained. These devices operate in a fully depleted state; expressions that describe the C-V relationship with a single gate electrode are derived and explored. The discussion presents an explanation of how surface and volume charge states each contribute to the C-V characteristic behavior. Application of this adapted C-V theory is then applied to the gated-diode, a novel device which has proven to be instrumental in charge state discrimination. Through this adaptation, the gated-diode is used to extract recombination-generation parameters isolated to the top surface, bottom surface and within the volume of the film. The methodology is developed through an exploration of devices fabricated on SOI and silicon-on-glass (SiOG) substrates, and furthers the understanding needed to improve material quality and device performance

Coherent Single Charge Transport in Molecular-Scale Silicon Nanowire Transistors

We report low-temperature electrical transport studies of molecule-scale silicon nanowires. Individual nanowires exhibit well-defined Coulomb blockade oscillations characteristic of charge addition to a single nanostructure with length scales up to at least 400 nm. Further studies demonstrate coherent charge transport through discrete single particle quantum levels extending the whole device, and show that the ground state spin configuration follows the Lieb-Mattis theorem. In addition, depletion of the nanowires suggests that phase coherent single-dot characteristics are accessible in a regime where correlations are strong.Comment: 4 pages and 4 figure

DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor

With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model .This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity . The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversion-mode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion / Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV / V

A hybrid metal/semiconductor electron pump for quantum metrology

Electron pumps capable of delivering a current higher than 100pA with sufficient accuracy are likely to become the direct mise en pratique of the possible new quantum definition of the ampere. Furthermore, they are essential for closing the quantum metrological triangle experiment which tests for possible corrections to the quantum relations linking e and h, the electron charge and the Planck constant, to voltage, resistance and current. We present here single-island hybrid metal/semiconductor transistor pumps which combine the simplicity and efficiency of Coulomb blockade in metals with the unsurpassed performances of silicon switches. Robust and simple pumping at 650MHz and 0.5K is demonstrated. The pumped current obtained over a voltage bias range of 1.4mV corresponds to a relative deviation of 5e-4 from the calculated value, well within the 1.5e-3 uncertainty of the measurement setup. Multi-charge pumping can be performed. The simple design fully integrated in an industrial CMOS process makes it an ideal candidate for national measurement institutes to realize and share a future quantum ampere

Two dimensional analytical threshold voltage modeling of dual material gate S-SOI mosfet

MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is the one of the most important and widely used semiconductor devices used in industry for various proposes. Two most important advantages of MOSFETs are their extremely low power dissipation and small area required for fabrication, i.e high packing density .With the advance of technology the feature sizes of MOSFETs are reduced continuously to increase the packing density of very large scale integration (VLSI) circuits. With continuous shrinkage of device geometrics on threshold voltage causes strong deviations from long channel behavior. The effect of such decrease in channel length is called SCE (Short channel Effect). A two dimensional Poisson equation needs to be solved in order to understand the effect of SCE.SCE (Short Channel Effect) is the effect of reduction in the channel length of MOSFET which results in significant differences from ideal characteristic like channel length modulation, carrier velocity saturation, two dimensional charge sharing, drain induced barrier lowering (DIBL), drain source series resistance and punch through. In order to minimize the effect of short channel effect various different modeling has been introduced. Among them DG MOSFET (Double Gate MOSFET), SOI MOSFET (Silicon-On Insulator MOSFET) are particularly important. In this thesis, a two dimensional threshold voltage model is developed for a Dual Material Gate Fully Depleted Strained Silicon on Insulator (DMG-FD-S-SOI) MOSFET considering the interface trap charges. The interface trap charges during the pre and post fabrication process are a common phenomenon, and these charges can’t be neglected in nano scale devices. For finding out the surface potential, parabolic approximation is utilized to solve 2D Poisson’s equation in the channel region. Further, the virtual cathode potential method is used to formulate the threshold voltage