Methods to Improve Applicability and Efficiency of Distributed Data-Centric Compute Frameworks

The success of modern applications depends on the insights they collect from their data repositories. Data repositories for such applications currently exceed exabytes and are rapidly increasing in size, as they collect data from varied sources - web applications, mobile phones, sensors and other connected devices. Distributed storage and data-centric compute frameworks have been invented to store and analyze these large datasets. This dissertation focuses on extending the applicability and improving the efficiency of distributed data-centric compute frameworks

Energy-efficient wireless communication

In this chapter we present an energy-efficient highly adaptive network interface architecture and a novel data link layer protocol for wireless networks that provides Quality of Service (QoS) support for diverse traffic types. Due to the dynamic nature of wireless networks, adaptations in bandwidth scheduling and error control are necessary to achieve energy efficiency and an acceptable quality of service. In our approach we apply adaptability through all layers of the protocol stack, and provide feedback to the applications. In this way the applications can adapt the data streams, and the network protocols can adapt the communication parameters

The Design of Medium Access Control (MAC) Protocols for Energy Efficient and QoS Provision in Wireless Sensor Networks

This thesis work focuses on innovative design of media access control (MAC) protocols in wireless sensor networks (WNSs). The characteristics of the WSN inquire that the network service design considers both energy efficiency and the associated application requirement. However, most existing protocols address only the issue of energy efficiency. In this thesis, a MAC protocol has been proposed (referred to as Q-MAC) that not only minimized the energy consumption in multi-hop WSNs, but also provides Quality of Service (QoS) by differentiating network services based on priority levels prescribed by different applications. The priority levels reflect the state of system resources including residual energy and queue occupancies. Q-MAC contains both intra- and inter- node arbitration mechanisms. The intra-node packet scheduling employs a multiple queuing architectures, and applies a scheduling scheme consisting of packet classification and weighted arbitration. We introduce the Power Conservation MACAW (PC-MACAW), a power-aware scheduling mechanism which, together with the Loosely Prioritized Random Access (LPRA) algorithm, govern the inter-node scheduling. Performance evaluation are conducted between Q-MAC and S-MAC with respect to two performance metrics: energy consumption and average latency. Simulation results indicate Q-MAC achieves comparable performance to that of S-MAC in non-prioritized traffic scenarios. When packets with different priorities are introduced, Q-MAC yields noticeable average latency differentiations between the classes of service, while preserving the same degree of energy consumption as that of S-MAC. Since the high density nature of WSN may introduce heavy traffic load and thus consume large amount of energy for communication, another MAC protocol, referred to as the Deployment-oriented MAC (D-MAC)has been further proposed. D-MAC minimalizes both sensing and communication redundancy by putting majority of redundant nodes into the sleep state. The idea is to establish a sensing and communication backbone covering the whole sensing field with the least sensing and communication redundancy. In specific, we use equal-size rectangular cells to partition the sensing field and chose the size of each cell in a way such that regardless of the actual location within the cell, a node can always sense the whole cell and communicate with all the nodes in neighboring cells. Once the sensing field has been partitioned using these cells, a localized Location-aware Selection Algorithm (LSA) is carried out to pick up only one node within each cell to be active for a fixed amount of period. This selection is energy-oriented, only nodes with a maximum energy will be on and the rest of nodes will be put into the sleep state once the selection process is over. To balance the energy consumption, the selection algorithm is periodically conducted until all the nodes are out of power. Simulation results indicated that D-MAC saves around 80% energy compared to that of S-MAC and Q-MAC, while maintaining 99% coverage. D-MAC is also superior to S-MAC and Q-MAC in terms of average latency. However, the use of GPS in D-MAC in identifying the nodes within the same cell, would cause extra cost and complexity for the design of sensor nodes

Embedded System Design

A unique feature of this open access textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This fourth edition has been updated and revised to reflect new trends and technologies, such as the importance of cyber-physical systems (CPS) and the Internet of things (IoT), the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues

Vector coprocessor sharing techniques for multicores: performance and energy gains

Vector Processors (VPs) created the breakthroughs needed for the emergence of computational science many years ago. All commercial computing architectures on the market today contain some form of vector or SIMD processing. Many high-performance and embedded applications, often dealing with streams of data, cannot efficiently utilize dedicated vector processors for various reasons: limited percentage of sustained vector code due to substantial flow control; inherent small parallelism or the frequent involvement of operating system tasks; varying vector length across applications or within a single application; data dependencies within short sequences of instructions, a problem further exacerbated without loop unrolling or other compiler optimization techniques. Additionally, existing rigid SIMD architectures cannot tolerate efficiently dynamic application environments with many cores that may require the runtime adjustment of assigned vector resources in order to operate at desired energy/performance levels. To simultaneously alleviate these drawbacks of rigid lane-based VP architectures, while also releasing on-chip real estate for other important design choices, the first part of this research proposes three architectural contexts for the implementation of a shared vector coprocessor in multicore processors. Sharing an expensive resource among multiple cores increases the efficiency of the functional units and the overall system throughput. The second part of the dissertation regards the evaluation and characterization of the three proposed shared vector architectures from the performance and power perspectives on an FPGA (Field-Programmable Gate Array) prototype. The third part of this work introduces performance and power estimation models based on observations deduced from the experimental results. The results show the opportunity to adaptively adjust the number of vector lanes assigned to individual cores or processing threads in order to minimize various energy-performance metrics on modern vector- capable multicore processors that run applications with dynamic workloads. Therefore, the fourth part of this research focuses on the development of a fine-to-coarse grain power management technique and a relevant adaptive hardware/software infrastructure which dynamically adjusts the assigned VP resources (number of vector lanes) in order to minimize the energy consumption for applications with dynamic workloads. In order to remove the inherent limitations imposed by FPGA technologies, the fifth part of this work consists of implementing an ASIC (Application Specific Integrated Circuit) version of the shared VP towards precise performance-energy studies involving high- performance vector processing in multicore environments