Removal of nitrogen pollutant from domestic wastewater

Water as a medium for waste transport would be easily contaminated by human activities. Many methods have been proposed to treat contaminated water to protect human health and biodiversity (Z. Daud et al., 2017). Due to upgrade the existing wastewater treatment plant facilities, the typically advanced technologies have been proposed to remove many types of pollutant, effectively (Tchobanoglous, Burton, & Stensel, 2004). The development of wastewater treatment plant needs to be considered leading economic indicators to have low operational and maintenance costs (Lewandowski, 2015; Shammas, Wang, & Wu, 2009). Aerobic digestion (AD) has been known since 1950 as biological wastewater treatment process to treat wastewater by removing the pollutants for instance colloids, organic compounds and suspended solids to avoid the excessive pollutants released into the receiving water (Shammas and Wang, 2007)

Kesan aplikasi pembelajaran berteraskan multimedia terhadap pelajar teknikal dari aspek gaya pembelajaran visual di politeknik Malaysia

Visual dalam pendidikan adalah pendekatan yang mampu melatih keupayaan pelajar untuk memahami sesuatu konsep pembelajaran yang baru dengan mudah mahupun meningkatkan tahap pemahaman. Kajian ini adalah bertujuan untuk mengenalpasti perkaitan diantara penggunaan aplikasi pembelajaran dengan gaya pembelajaran visual pelajar dalam matapelajaran Computer Networking Fundamentals. Responden kajian ini adalah terdiri daripada pelajar semester 5 daripada 2 buah Politeknik iaitu Politeknik Ibrahim Sultan, Johor, dan Politeknik Port Dickson, Negeri Sembilan yang mengambil matapelajaran Computer Networking Fundamentals (EC301) . Seramai 19 responden yang diambil sebagai kumpulan rawatan daripada Politeknik Ibrahim Sultan (PIS) dan seramai 21 responden lagi berfungsi sebagai kumpulan kawalan daripada Politeknik Port Dickson (PPD). Terdapat 3 instrumen yang digunakan untuk menjalankan kajian ini. Instrumen pertama adalah aplikasi pembelajaran bagi matapelajaran Computer Networking Fundamentals (EC301) yang digunakan oleh kumpulan rawatan, borang kaji selidik untuk mengenalpasti gaya pembelajaran setiap responden, dan intrumen yang ketiga adalah set ujian penilaian (ujian pra dan ujian pasca) bagi menilai tahap pencapaian kesemua responden. Data dianalisis menggunakan Analisis ANCOVA dan hasil kajian mendapati bahawa, pelajar yang menggunakan aplikasi pembelajaran dan disesuaikan dengan gaya pembelajaran visual (A_V) mencapai skor min markah yang paling tinggi iaitu 10.194 berbanding dengan kategori pelajar yang bukan bergaya pembelajaran visual dan tidak menggunakan aplikasi pembelajaran yang masing-masing hanya mencapai skor min 9.417 (A_BV), 4.950 (BA_BV) dan 3.646 (BA_V). Berasaskan kepada hasil dapatan ini, satu kerangka perlaksanaan telah di syorkan dengan menggabungkan intervensi aplikasi pembelajaran dengan elemen gaya pembelajaran visual bagi meningkatkan daya kefahaman pelajar semasa proses pengajaran dan pembelajaran

Subthreshold circuits: Design, implementation and application

Digital circuits operating in the subthreshold region of the transistor are being used as an ideal option for ultra low power complementary metal-oxide-semiconductor (CMOS) design. The use of subthreshold circuit design in cryptographic systems is gaining importance as a counter measure to power analysis attacks. A power analysis attack is a non-invasive side channel attack in which the power consumption of the cryptographic system can be analyzed to retrieve the encrypted data. A number of techniques to increase the resistance to power attacks have been proposed at algorithmic and hardware levels, but these techniques suffer from large area and power overheads. The main aim of this research is to understand the viability of implementing subthreshold systems for cryptographic applications. Standard cell libraries in subthreshold are designed and a methodology to identify the minimum energy point, aspect ratio, frequency range and operating voltage for CMOS standard cells is defined. As scalar multiplication is the fundamental operation in elliptic curve cryptographic systems, a digit-level gaussian normal basis (GNB) multiplier is implemented using the aforementioned standard cells. A similar standard-cell library is designed for the multiplier to operate in the superthreshold regime. The subthreshold and superthreshold multipliers are then subjected to a differential power analysis attack. Power performance and signal-to-noise ratio (SNR) of both these systems are compared to evaluate the usefulness of the subthreshold design. The power consumption of the subthreshold multiplier is 4.554 uW, the speed of the multiplier is 65.1 KHz and the SNR is 40 dB. The superthreshold multiplier has a power consumption of 4.005 mW, the speed of the multiplier is 330 MHz and the SNR is 200 dB. Reduced power consumption, hence reduced SNR, increases the resistance of the subthreshold multiplier against power analysis attacks. (Refer to PDF for exact formulas)

DESIGN OF THREE-INPUT XOR/XNORS GATES BASED ON SCDM TECHNIQUE FOR REDUCED AREA AND LESS ENERGY

In this paper we are proposing new systematic cell design methodology based efficient two three-input XOR/XNOR circuits in hybrid CMOS logic style. These XOR gates are used to design Full Adder with less area and less energy. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. We start with selecting a basic cell including three independent inputs and two complementary outputs. Next we combine this basic cell with various correction and optimization techniques to build a perfect XOR-XNOR circuit with full swing operation. The performance of the XOR-XNOR circuits  based on 90 nm CMOS technology process models at all range of the supply voltage is evaluated by the comparison of the simulation results obtained from MICRO WIND. Simulation output results shows that the proposed design consumes less power and less area than the conventional design

64 x 64 Bit Multiplier Using Pass Logic

ABSTRACT Due to the rapid progress in the field of VLSI, improvements in speed, power and area are quite evident. Research and development in this field are motivated by growing markets of portable mobile devices such as personal multimedia players, cellular phones, digital camcorders and digital cameras. Among the recently popular logic families, pass transistor logic is promising for low power applications as compared to conventional static CMOS because of lower transistor count. This thesis proposes four novel designs for Booth encoder and selector logic using pass logic principles. These new designs are implemented and used to build a 64 x 64-bit multiplier. The proposed Booth encoder and selector logic are competitive with the existing and shows substantial reduction in transistor count. It also shows improvements in delay when compared to two of the three published works

Energy Efficient CNTFET Based Full Adder Using Hybrid Logic

Full Adder is the basic element for arithmetic operations used in Very Large Scale Integrated (VLSI) circuits, therefore, optimization of 1-bit full adder cell improves the overall performance of electronic devices. Due to unique mechanical and electrical characteristics, carbon nanotube field effect transistors (CNTFET) are found to be the most suitable alternative for metal oxide field effect transistor (MOSFET). CNTFET transistor utilizes carbon nanotube (CNT) in the channel region. In this paper, high speed, low power and reduced transistor count full adder cell using CNTFET 32nm technology is presented. Two input full swing XOR gate is designed using 4 transistors which is further used to generate Sum and Carry output signals with the help of Gate-Diffusion-Input (GDI) Technique thus reducing the number of transistors involved. Proposed design simulated in Cadence Virtuoso with 32nm CNTFET technology and results is better design as compared to existing circuits in terms of Power, Delay, Power-Delay-Product (PDP), Energy Consumption and Energy-Delay-Product (EDP)

Design and simulation of a new QCA-based low-power universal gate

Quantum-dot Cellular Automata (QCA) is recognized in electronics for its low power consumption and high-density capabilities, emerging as a potential substitute for CMOS technology. GDI (Gate Diffusion Input) technology is featured as an innovative approach for enhancing power efficiency and spatial optimization in digital circuits. This study introduces an advanced four-input Improved Gate Diffusion Input (IGDI) design specifically for QCA technology as a universal gate. A key feature of the proposed 10-cell block is the absence of cross-wiring, which significantly enhances the circuit’s operational efficiency. Its universal cell nature allows for the carrying out of various logical gates by merely altering input values, without necessitating any structural redesign. The proposed design showcases notable advancements over prior models, including a reduced cell count by 17%, a 29% decrease in total energy usage, and a 44% reduction in average energy loss. This innovative IGDI design efficiently executes 21 combinational and various sequential functions. Simulations in 18 nm technology, accompanied by energy consumption analyses, demonstrate this design’s superior performance compared to existing models in key areas such as multiplexers, comparators, and memory circuits, alongside a significant reduction in cell count