In this paper we are proposing new systematic cell design methodology based efficient two three-input XOR/XNOR circuits in hybrid CMOS logic style. These XOR gates are used to design Full Adder with less area and less energy. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. We start with selecting a basic cell including three independent inputs and two complementary outputs. Next we combine this basic cell with various correction and optimization techniques to build a perfect XOR-XNOR circuit with full swing operation. The performance of the XOR-XNOR circuits  based on 90 nm CMOS technology process models at all range of the supply voltage is evaluated by the comparison of the simulation results obtained from MICRO WIND. Simulation output results shows that the proposed design consumes less power and less area than the conventional design

Prasad, Kanakala Manikanta

Veera Manikanth, Mukkapati

International Journal of Innovative Technology and Research (IJITR)

Mukkupati Veera Manikanth* et al. (IJITR) INTERNATIONAL JOURNAL OF INNOVATIVE TECHNOLOGY AND RESEARCH  Volume No.5, Issue No.3, April – May 2017, 6305-6308.  2320 –5547 @ 2013-2017 http://www.ijitr.com All rights Reserved.  Page | 6305  Design Of Three-Input XOR/XNORS Gates Based On SCDM Technique For Reduced Area And Less Energy Mr. MUKKAPATI.VEERA MANIKANTH Assistant professor, Kakinada Institute of Engineering and Technology KANAKALA MANIKANTA PRASAD M.Tech., Kakinada Institute of Engineering and Technology Abstract: In this paper we are proposing new systematic cell design methodology based efficient two three-input XOR/XNOR circuits in hybrid CMOS logic style. These XOR gates are used to design Full Adder with less area and less energy. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. We start with selecting a basic cell including three independent inputs and two complementary outputs. Next we combine this basic cell with various correction and optimization techniques to build a perfect XOR-XNOR circuit with full swing operation. The performance of the XOR-XNOR circuits  based on 90 nm CMOS technology process models at all range of the supply voltage is evaluated by the comparison of the simulation results obtained from MICRO WIND. Simulation output results shows that the proposed design consumes less power and less area than the conventional design. Index Terms—Binary Decision Diagram Applications; Energy Efficiency; Hybrid-CMOS Logic Style; Systematic Design Methodology; Three-Input XOR/XNOR Circuits; I. INTRODUCTION With the rapid growth of portable electronic devices, it is becoming a critical challenge to design low-power, high-speed (LPHS) circuits that occupy small chip areas. We see many published papers that compete in designing better circuits. In this paper we are proposing low area and less energy exclusive-OR (XOR) and exclusive-NOR (XNOR) gates are the essential parts of several digital systems and are highly used in very large scale integration (VLSI) systems such as parity checkers, comparators, crypto processors, arithmetic and logic circuits, test pattern generators, especially in Full adder module as Sum output that is 3-input XOR and so forth. In most of these systems, XOR and XNOR gates constitute a part of the critical path of the system, which significantly affects the worst-case delay and the overall performance of the system. An optimized design is desired to avoid any degradation on the output voltage, consume less power, and have less delay in critical path with low supply voltage as we scale toward deep sub-micron technology. Other desired features for the design are to have a small number of transistors to implement the circuit. In particular, for XOR and XNOR circuits, the simultaneous generation of the two-non skewed outputs is highly desirable. As known, the switching speed of the balanced XOR and XNOR functions, comparing with those designs that use an inverter to generate the complement signal, is increased by eliminating the inverter from the critical path. Thus the design methodology for 3-input XOR/XNOR circuits is introduced. II. PREVIOUS WORK The state-of-the art issues in this brief can be divided into two categories as they are extracted from the   topic:    1)   conventional   three   input   XOR    and 2) methodologies. Most of the designed SUMs have been produced jointly or by cascading some modules. The cascaded modules derived from reformulations of the Boolean functions. III. SCDM FOR THREE-INPUT XOR/XNOR CIRCUITS The methodology for three-input XOR/XNORs is presented in this section according to the flowchart shown in Fig. 1(a). The design path is started by EBC systematic generation. In this step, general design goals are considered that the most distinctive ones are generating fairly balanced outputs, symmetric and power-ground-free structure, less transistors in the critical path, as well as sharing common sub circuit. Systematic generation process of. In the remaining steps, the methodology offers opportunity to strive toward an assigned design target. Two of these steps include wisely selection of mechanisms and basic cells from PDP point of view. An in-depth analysis for the selection Fig. in terms of Mukkupati Veera Manikanth* et al. (IJITR) INTERNATIONAL JOURNAL OF INNOVATIVE TECHNOLOGY AND RESEARCH  Volume No.5, Issue No.3, April – May 2017, 6305-6308.  2320 –5547 @ 2013-2017 http://www.ijitr.com All rights Reserved.  Page | 6306  PDP. In the last step, in order to put the resultant circuits in proper state, a sizing algorithm consistent with the methodology is indispensable.  Fig. 1. (a) SCDM process for designing efficient three- input XOR/XNORs. (b) BDT representation of three-input XOR/XNOR function. (c) Applying reduction rules. (d) Substitution and disjointing. (e) EBC IV. INTRODUCTION OF THE STRUCTURE OF THREE- INPUT XOR/XNOR CIRCUITS WITH THE AVERAGE PDP The three input XOR/XNOR gates are realized using the transmission gate logic. Thus the transmission gate is a design of parallel connection of PMOS and NMOS. By using this gate design, the three input XOR/XNOR gates are realized and thus the logical operations of gate are achieved in the result. The three input XOR/XNOR circuits XO4, X07 is shown in the Fig.2.   Fig. 2. Three-input XOR/XNOR circuits, XO4, XO7 To control the capacity of this brief, only the simulation results of the conventional and three of the best proposed circuits in terms of average PDP, XO4, XO7. The ascending order of delay, which is the maximum delay between all the possible transitions, as well as PDP it is apparent that among the circuits XO4 and XO7 have the reduced delays. The circuit of XO7 has slightly less delay than the XO4 at lower supply voltages. However, the trend will reverse at higher supply voltages. Hernandez1 has the second position. The Hernandez1. In the common circumstances, the circuits utilizing FP, such as XO7 is superior to the circuits utilizing BP like XO10, which is compatible with the delay trend of mechanisms. The circuits with C2 like XO7 also perform better than the circuits with C1. Since bootstrap technique saves the internal node voltages, the average power dissipation underneath different supply voltages shows that PB has less power dissipation in common situation. XO7 employing FP with regard to average power. According to the PDP trend, the ability of TG to provide full-swing leads to the best circuit with optimum performance and drivability as among the circuits, XO4 has the lowest PDP. After that, circuit XO7 have the second position. PDP of XO7 is less than that of XO4 for lower voltages but the movement reverses for higher voltages. Hence, from energy point of view, XO7 is an enhanced choice. Mukkupati Veera Manikanth* et al. (IJITR) INTERNATIONAL JOURNAL OF INNOVATIVE TECHNOLOGY AND RESEARCH  Volume No.5, Issue No.3, April – May 2017, 6305-6308.  2320 –5547 @ 2013-2017 http://www.ijitr.com All rights Reserved.  Page | 6307  The circuits, such as XO7 using FP outperform the circuits using feedback. The circuits with C2 like XO7 offer less PDP than the circuits with C1. V. OUTPUT RESULTS  Fig3. Schematic diagram of XO4 Above figure shows the schematic diagram for three input XOR/XNOR by using the proposed design methodology. The schematic is performed using DSCH software. Figure 4 and figure 5 shows the layout and simulation output for the proposed design. Which is designed using MICROWIND software as mentioned earlier.  Figure 4: Layout design  Figure 5: Simulation output VI. CONCLUSION To design a three input XOR/XNOR gate and  the analytical expression of optimum frequency and supply voltage under minimum energy condition has been verified through simulation in 90-nm technology. The performance of the proposed circuits can operate at low voltages, and have good output levels. According to the simulation results, the proposed circuit offers a better result and more competitive than other design. It offers the lowest power dissipation at a low supply voltage. It has a good driving capability with good output signal in all input combinations and well performance especially in low supply voltage compared to the previous designs. Thus, the proposed circuit is suitable for low-voltage and low-power application. In future work 8-bit adder architecture based on the design of three-input XOR/XNOR gate will be designed. The power consumption and delay performance are calculated and compared with the existing system. VII. REFERENCES [1] C.-K. Tung, S.-H. Shieh, and C.-H. Cheng, “Low- power high-speed full adder for portable electronic applications,” Electron. Lett., vol. 49, no. 17, pp. 1063– 1064, Aug. 2013. [2] M. Aguirre-Hernandez and M. Linares-Aranda, “CMOS full-adders for energy-efficient arithmetic applications,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp. 718–721, Apr. 2011. [3] M. H. Moaiyeri, R. F. Mirzaee, K. Navi, T. Nikoubin, and O. Kavehei, “Novel direct designs for 3- input XOR function for low-power and highspeed applications,” Int. J. Electron., vol. 97, no. 6, pp. 647– 662, 2010. [4] S. Goel, M. A. Elgamel, M. A. Bayoumi, and Y. Hanafy, “Design methodologies for high-performance noise-tolerant XOR-XNOR circuits,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 4, pp. 867–878, Apr. 2006. [5] S. Goel, A. Kumar, and M. Bayoumi, “Design of robust, energy-efficient full adders for deep- submicrometer design using hybrid-CMOS logic style,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 1309–1321, Dec. 2006. [6] C.-H. Chang, J. Gu, and M. Zhang, “A review of 0.18-μm full adder performances for tree structured arithmetic circuits,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686–695, Jun. 2005. [7] T. Nikoubin, M. Grailoo, and S. H. Mozafari, “Cell design methodology based on Mukkupati Veera Manikanth* et al. (IJITR) INTERNATIONAL JOURNAL OF INNOVATIVE TECHNOLOGY AND RESEARCH  Volume No.5, Issue No.3, April – May 2017, 6305-6308.  2320 –5547 @ 2013-2017 http://www.ijitr.com All rights Reserved.  Page | 6308  transmission gate for low- power high-speed balanced XOR-XNOR circuits in hybrid-CMOS logic style,” J. Low Power Electron., vol. 6, no. 4, pp. 503–512, 2010. [8] T. Nikoubin, A. Baniasadi, F. Eslami, and K. Navi, “A new cell design methodology for balanced XOR- XNOR circuits for hybrid- CMOS logic,” J. Low Power Electron., vol. 5, no. 4, pp. 474–483, 2009. AUTHOR’s PROFILE  Mr.    MUKKAPATI.    VEERA   MANIKANTH hailed from Kakinada. He is working as an Assistant Professor Department of ECE at Kakinada Institute of Engineering and Technology(KIET). He completed his M.Tech. in Embedded Systems. His research interest in Analog layout Design, RTL, COMS, Embedded Systems, Arduino Processors.   Mr.    KANAKALA    MANIKANTA    PRASAD, hailed from Yanam. He is pursuing his M.Tech. in VLSI Design, Department of ECE at  Kakinada Institute of Engineering and Technology(KIET). He completed his B.Tech. in Electronics and communication Engineering. His research interest in Digital VLSI Design, RTL Design, Synthesis and physical design. 

DESIGN OF THREE-INPUT XOR/XNORS GATES BASED ON SCDM TECHNIQUE FOR REDUCED AREA AND LESS ENERGY

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DESIGN OF THREE-INPUT XOR/XNORS GATES BASED ON SCDM TECHNIQUE FOR REDUCED AREA AND LESS ENERGY

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