Delay and Power Reduction in Deep Submicron Buses

As technology scales down, coupling between nodes of the circuits increases and becomes an important factor in interconnection analysis. In many cases like the deep submicron technology (DSM), the coupling between lines (inter-wire capacitance) is strong and the energy consumption caused by parasitic capacitance is non-negligible. In this work, we employ the differential low-weight encoding [1] to reduce energy and delay (transmission cost) on DSM buses. We propose an enumeration method that reduces the encoder table-size from O(2n) words to O(n) words, for an n-bit DSM bus, and so reduces the memory complexity significantly and facilitates energy and delay reduction due to addressing and fetching data from large lookup tables. We modify the energy and delay equations for DSM buses and develop new representations in terms of number of the same and opposite direction transitions on the bus and use them in our interconnect analysis. We also use these equations to develop formulas for computing the mean transmission cost per bit on DSM buses for both differential low-weight encoding and uncoded schemes. Using the interconnect analysis, we compute a help codeword (from the set of unselected codewords) on the fly and assign to each selected codeword. This low complexity step consists of simple operations and enables us to gain more cost reduction without increasing the table size or number of the bus lines. The simulation results for 16-bit, 32-bit and 64-bit buses at maximum rate (only one extra line added) show that the proposed encoding scheme achieves more than 10% cost reduction, and performs more than 2.5% better than to the original differential low-weight scheme, in the worst case

Multi-level optical signal generation using a segmented-electrode InP IQ-MZM with integrated CMOS binary drivers

We present a segmented-electrode InP IQ-MZM, capable of multi-level optical signal generation (5-bit per I/Q arm) by employing direct digital drive from integrated, low-power (1W) CMOS binary drivers. Programmable, multi-level operation is demonstrated experimentally on one MZM of the device

Spin-Based Neuron Model with Domain Wall Magnets as Synapse

We present artificial neural network design using spin devices that achieves ultra low voltage operation, low power consumption, high speed, and high integration density. We employ spin torque switched nano-magnets for modelling neuron and domain wall magnets for compact, programmable synapses. The spin based neuron-synapse units operate locally at ultra low supply voltage of 30mV resulting in low computation power. CMOS based inter-neuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics based models developed for the spin devices. Simulation results for character recognition as a benchmark application shows 95% lower power consumption as compared to 45nm CMOS design

Environmental Quality Laboratory Research Report, 1985-1987

The Environmental Quality Laboratory at Caltech is a center for research on large-scale systems problems of natural resources and environmental quality. The principal areas of investigation at EQL are: 1. Air quality management. 2. Water resources and water quality management. 3. Control of hazardous substances in the environment. 4. Energy policy, including regulation, conservation and energy-environment tradeoffs. 5. Resources policy (other than energy); residuals management. EQL research includes technical assessments, computer modeling, studies of environmental control options, policy analyses, and research on important components of the large-scale systems. Field work is also undertaken at EQL, some in collaboration with other organizations, to provide critical data needed for evaluation of systems concepts and models. EQL's objectives are as follows: 1. To do systematic studies of environmental and resources problems. The results of these studies, including the clarification of policy alternatives, are communicated to decision-makers in government and industry, to the research community, and to the public. As an organization, EQL refrains from advocating particular policies, but seeks to point out the implications of the various policy alternatives. 2. To contribute to the education and training of people in these areas through involvement of predoctoral students, postdoctoral fellows, and visiting faculty members in EQL activities. This educational effort is just as important as the results of the studies themselves, and should make lasting contributions to the nation's ability to solve its environmental and resources problems. The work at EQL goes beyond the usual academic research in that it tries to organize and develop the knowledge necessary to clarify society's alternatives by integrating relevant disciplines. EQL works on solving problems of specific localities when there is a strong element of public interest or educational value, or the concepts and results are applicable to other places. The research of EQL during this period was done under the supervision of faculty members in Environmental Engineering Science, Chemical Engineering, and Social Science. This research report covers the period from October 1985 through September 1987. The publications listed under the individual project descriptions are the new ones for the reporting period

Roadmap on semiconductor-cell biointerfaces.

This roadmap outlines the role semiconductor-based materials play in understanding the complex biophysical dynamics at multiple length scales, as well as the design and implementation of next-generation electronic, optoelectronic, and mechanical devices for biointerfaces. The roadmap emphasizes the advantages of semiconductor building blocks in interfacing, monitoring, and manipulating the activity of biological components, and discusses the possibility of using active semiconductor-cell interfaces for discovering new signaling processes in the biological world

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.Ph.D.Committee Chair: Kim, Jongman; Committee Member: Kang, Sung Ha; Committee Member: Lee, Chang-Ho; Committee Member: Mukhopadhyay, Saibal; Committee Member: Tentzeris, Emmanouil