An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Systems with Massive Number of Antennas: Distributed Approaches

As 5G is entering maturity, the research interest has shifted towards 6G, and specially the new use cases that the future telecommunication infrastructure needs to support. These new use cases encompass much higher requirements, specifically: higher communication data-rates, larger number of users, higher accuracy in localization, possibility to wirelessly charge devices, among others.The radio access network (RAN) has already gone through an evolution on the path towards 5G. One of the main changes was a large increment of the number of antennas in the base-station. Some of them may even reach 100 elements, in what is commonly referred as Massive MIMO. New proposals for 6G RAN point in the direction of continuing this path of increasing the number of antennas, and locate them throughout a certain area of service. Different technologies have been proposed in this direction, such as: cell-free Massive MIMO, distributed MIMO, and large intelligent surface (LIS). In this thesis we focus on LIS, whose conducted theoretical studies promise the fulfillment of the aforementioned requirements.While the theoretical capabilities of LIS have been conveniently analyzed, little has been done in terms of implementing this type of systems. When the number of antennas grow to hundreds or thousands, there are numerous challenges that need to be solved for a successful implementation. The most critical challenges are the interconnection data-rate and the computational complexity.In the present thesis we introduce the implementation challenges, and show that centralized processing architectures are no longer adequate for this type of systems. We also present different distributed processing architectures and show the benefits of this type of schemes. This work aims at giving a system-design guideline that helps the system designer to make the right decisions when designing these type of systems. For that, we provide algorithms, performance analysis and comparisons, including first order evaluation of the interconnection data-rate, processing latency, memory and energy consumption. These numbers are based on models and available data in the literature. Exact values depend on the selected technology, and will be accurately determined after building and testing these type of systems.The thesis concentrates mostly on the topic of communication, with additional exploration of other areas, such as localization. In case of localization, we benefit from the high spatial resolution of a very-large array that provides very rich channel state information (CSI). A CSI-based fingerprinting via neural network technique is selected for this case with promising results. As the communication and localization services are based on the acquisition of CSI, we foresee a common system architecture capable of supporting both cases. Further work in this direction is recommended, with the possibility of including other applications such as sensing.The obtained results indicate that the implementation of these very-large array systems is feasible, but the challenges are numerous. The proposed solutions provide encouraging results that need to be verified with hardware implementations and real measurements

Wireless Transceivers for Implantable Microsystems.

In this thesis, we present the first-ever fully integrated mm3 low-power biomedical transceiver with 1 meter of range that is powered by a mm2 thin-film battery. The transceiver is targeted for biomedical implants where size and energy constraints dictated by application make design challenging. Despite all the previous work in RFID tags, form factor of such radios is incompatible with mm3 biomedical implants. The proposed transceiver bridges this gap by providing a compact low-power solution that can run off small thin-film batteries and can be stacked with other system components in a 3D fashion. On the sensor-to-external side, we proposed a novel FSK architecture based on dual-resonator LC oscillators to mitigate unwanted overlap of two FSK tones’ phase noise spectrum. Due to inherent complexity of such systems, fourth order dual-resonator oscillators can exhibit instable operation. We mathematically modeled the instability and derive design conditions for stable oscillations. Through simulation and measurements, validity of derived models was confirmed. Together with other low-power system blocks, the transmitter was successfully implanted in live mouse and in-vivo measurements were performed to confirm successful transmission of vital signals through organic tissue. The integrated transmitter achieved a bit-error-rate of 10-6 at 10cm with 4.7nJ/bit energy consumption. On the external-to-sensor link, we proposed a new protocol to lower receiver peak power, which is highly limited due to small size of mm3 microsystem battery. In the proposed protocol, sending same data multiple times drastically relaxes jitter requirement on the sensor side at the cost of increased power consumption on the external side without increasing peak power radiated by the external unit. The receiver also uses a dual-coil LNA to improve range by 22% with only 11% area overhead. An asynchronous controller manages protocol timing and limits total monitoring current to 43nA. The fabricated receiver consumes 1.6nJ/bit at 40kbps while positioned 1m away from a 2W source.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/102458/1/ghaed_1.pd

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Occupancy Detection using Wireless Sensor Network in Indoor Environment

Occupancy detection plays an important role in many smart buildings such as reducing building energy usage by controlling heating, ventilation and air conditioning (HVAC) systems, monitoring systems and managing lighting systems, tracking people in hospitals for medical issues, advertising to people in malls, and to search and rescue missions. The global positioning system (GPS) is used most widely as a localization system but highly inaccurate for indoor applications. The indoor environment is difficult to handle because along with the loss of signals, privacy is a major concern. Indoor tracking has many aspects in common with sensor localization in Wireless Sensor Networks (WSN). The contribution of this work is the demonstration of a nonintrusive approach to detect an occupancy in a building using wireless sensor networks to detect energy from cell phones in a secure facility and perform indoor localization based on the minimum mean square error (MMSE). To estimate the occupancy, the detected cellular signals information such as signal amplitude, frequency, power and detection time is sent to a fusion server, matched the detected signals by time and channel information, performed localization to estimate a location, and finally estimated the occupancy of rooms in a building from the estimated locations

Physical Layer Modeling and Optimization of Silicon Photonic Interconnection Networks

The progressive blooming of silicon photonics technology (SiP) has indicated that optical interconnects may substitute the electrical wires for data movement over short distances in the future. Silicon Photonics platform has been the subject of intensive research for more than a decade now and its prospects continue to emerge as it enjoys the maturity of CMOS manufacturing industry. SiP foundries all over the world and particularly in the US (AIM Photonics) have been developing reliable photonic design kits (PDKs) that include fundamental SiP building blocks such as wavelength selective modulators and tunable filters. Microring resonators (MRR) are hailed as the most compact devices that can perform both modulation and demodulation in a wavelength division multiplexed (WDM) transceiver design. Although the use of WDM can reduce the number of fibers carrying data, it also makes the design of transceivers challenging. It is probably acceptable to achieve compactness at the expense of somewhat higher transceiver cost and power consumption. Nevertheless, these two metrics should remain close to their roadmap values for Datacom applications. An increase of an order of magnitude is clearly not acceptable. For example costs relative to bandwidth for an optical link in a data center interconnect will have to decrease from the current $5/Gbps down to <$1/Gbps. Additionally, the transceiver itself must remain compact. The optical properties of SiP devices are subject to various design considerations, operation conditions, and optimization procedures. In this thesis, the general goal is to develop mathematical models that can accurately describe the thermo-optical and electro-optical behavior of individual SiP devices and then use these models to perform optimization on the parameters of such devices to maximize the capabilities of photonic links or photonic switch fabrics for datacom applications. In Chapter 1, Introduction, we first provide an overview of the current state of the optical transceivers for data centers and datacom applications. Four main categories for optical interfaces (Pluggable transceivers, On-board optics, Co-packaged optics, monolithic integration) are briefly discussed. The structure of a silicon photonic link is also briefly introduced. Then the direction is shifted towards optical switching technologies where various technologies such as free space MEMS, liquid crystal on silicon (LCOS), SOA-based switches, and silicon-based switches are explored. In Chapter 2, Silicon Photonic Waveguides, we present an extensive study of the silicon-on-insulator (SOI) waveguides that are the basic building blocks of all of the SiP devices. The dispersion of Si and SiO2 is modeled with Sellmiere equation for the wavelength range 1500–1600 nm and then is used to calculate the TE and TM modes of a 2D slab waveguide. There are two reasons that 2D waveguides are studied: first, the modes of these waveguides have closed form solutions and the modes of 3D waveguides can be approximated from 2D waveguides based on the effective index method. Second, when the coupling of waveguides is studied and the concept of curvature function of coupling is developed, the coupled modes of 2D waveguides are used to show that this approach has some inherent small error due to the discretization of the nonuniform coupling. This chapter finishes by describing the coefficients of the sensitivity of optical modes of the waveguides to the geometrical and material parameters. Perturbation theory is briefly presented as a way to analytically examine the impact of small perturbations on the effective index of the modes. In Chapter 3, Compact Modeling Approach, the concept of scattering matrix of a multi-port silicon photonic device is presented. The elements of the S-matrix are complex numbers that relate the amplitude and phase relationships of the optical models in the input and output ports. Based on the scattering matrix modeling of silicon photonics devices, two methods of solving photonic circuits are developed: the first one is based on the iteration for linear circuits. The second approach is based on the construction of an equivalent signal flow graph (SFG) for the circuit. We show that the SFG approach is very efficient for circuits involving microring resonator structures. Not only SFG can provide the solution for the transmission, it also provides the signal paths and the closed-form solution based on the Mason’s graph formula. We also show how the SFG method can be utilized to formulate the backscattering effects inside a ring resonator. In Chapter 4, Scalability of Silicon Photonic Switch Fabrics, we develop the models for electro-optic Mach-Zehnder switch elements (2×2). For the electro-optic properties, the empirical Soref’s equations are used to characterize how the loss and index of silicon changes when the charge carrier density is changed. We then use our photonic circuit solver based on the iteration method to find accurate result of light propagation in large-scale switch topologies (e.g. 4×4, and 8×8). The concept of advanced path mapping based on physical layer evaluation of the switch fabric is introduced and used to develop the optimum routing tables for 4×4 and 8×8 Benes switch topologies. In Chapter 5, Design space of Microring Resonators, we introduce the concept of curvature function of coupling to mathematically characterize the coupling coefficient of a ring resonator to a waveguide as a function of the geometrical parameters (ring radius, coupling gap, width and height of waveguides) and the wavelength. Extensive 2D and 3D FDTD simulations are carried out to validate our modeling approach. Experimental demonstrations are also used to not only further validate our modeling of coupling, but also to extract an empirical power-law model for the bending loss of the ring resonators as a function the radius. By combining these models, we for the first time present a full characterization of the design space of microring resonators. Moreover, the value of this discussion will be further apparent when the scalability of a silicon photonic link is studied. We will show that the FSR of the rings determines the optical bandwidth but it also impacts the properties of the ring resonators. In Chapter 6, Thermo-optic Efficiency of Microheaters, we develop analytical models for the thermo-optic properties of SiP waveguides. For the thermo-optic properties, the concept of thermal impulse response is mathematically developed for integrated micro-heaters. The thermal impulse response is a key function that determines the tradeoff between heating efficiency and heating speed (thermal bandwidth), as well as allows us to predict the pulse-width-modulation (PWM) optical response of the heater-waveguide system. One of the motivations behind this study was to find the highest possible efficiency for thermal tuning of microring resonators to use it in the evaluation of the energy consumption of a photonic link. The results indicate 2 nm/mW which is in agreement with the trends that we see in the literature. In Chapter 7, Crosstalk Penalty, we theoretically and experimentally investigate the optical crosstalk effects in microring-based silicon photonic interconnects. Both inter-channel crosstalk and intra-channel crosstalk are investigated and approximate equations are developed for their corresponding power penalties. Inclusion of the inter-channel crosstalk is an important part of our final analysis of a silicon photonic link. In Chapter 8, Scalability of Silicon Photonic Links, we present the analysis of a WDM silicon photonics point-to-point link based on microring modulators and microring wavelength filters. Our approach is based on the power penalty analysis of non-return-to-zero (NRZ) signals and Gaussian noise statistics. All the necessary equations for the optical power penalty calculations are presented for microring modulators and filters. The first part of the analysis is based on various ideal assumptions which lead to a maximum capacity of 2.1 Tb/s for the link. The second part of the analysis is carried out with more realistic assumptions on the photonic elements in the link, culminating in a maximum throughput of 800 Gb/s. We also provide estimations of the energy/bit metric of such links based on the optimized models of electronic circuits in 65 nm CMOS technology