Автоматизоване проєктування вбудованих систем цифрового оброблення сигналів на платформі SoC

The object of the study is the procedures for automated design and analysis of digital signal processing algorithms on the SoC technology platform. The subject of the study is models, methods and procedures for designing and optimal selection of SoC components for the implementation of digital signal processing algorithms for audio spectrum. The aim of the study is to develop models and procedures for determining the possibilities of a compromise distribution of signal processing algorithm computations in the cycle of computer-aided design on the SoC technology platform in terms of performance and the feasibility of using hardware and software algorithms realization. The article solves the following tasks: consideration of the procedures for interacting the processor core with programmable logic as part of system-on-chip systems; development of procedures for computer-aided design and analysis of signal processing systems using programming languages and hardware description languages for the implementation of embedded systems. The following methods are being used: implementation of digital signal processing algorithms in the C programming language and high-level synthesis tools for realizing IP blocks, diagnostic experiment by generating test signal patterns, and analysis of the processing results at the system output. The results achieved. Based on the analysis of the procedures for the interaction of the processor core and programmable logic on the selected SoC platform, a model of the audio spectrum signal processing system is designed. The practical implementation was performed based on the Vivado/Vitis/Vitis HLS CAD tool stack. The proposed model was verified using a programmable test signal generator and analyzing the obtained characteristics of digital filters at the system output. Conclusions. The article analyzes the principles of designing embedded information processing systems implemented in system-on-chip. The principles of building and analyzing digital signal processing systems based on system-on-chip containing programmable logic and processor parts are considered. The developed methods have been tested on the algorithms of CIC and FIR filters on the technological platform of SoC FPGA of the ZYNQ-7000 family of Xilinx company.Об’єктом дослідження є процедури автоматизованого проєктування та аналізу алгоритмів цифрового оброблення сигналів на технологічній платформі SoC. Предмет вивчення – моделі, методи та процедури проєктування та оптимального вибору компонентів SoC для реалізації алгоритмів цифрового оброблення сигналів аудіоспектра. Метою дослідження є розроблення моделей та процедур для визначення можливостей компромісного розподілу обчислень алгоритмів оброблення сигналів у циклі автоматизованого проєктування на технологічній платформі SoC за критерієм продуктивності й доцільності використання апаратної та програмної реалізації алгоритмів. У статті розв’язуються такі завдання: розгляд процедур взаємодії процесорного ядра з програмованою логікою у складі систем на кристалі; розвиток процедур автоматизованого проєктування та аналізу систем оброблення сигналів із використанням мов програмування та мов опису апаратури для реалізації вбудованих систем. Упроваджуються такі методи: імплементація алгоритмів цифрового оброблення сигналів мовою програмування С та інструментів високорівневого синтезу для реалізації IP-блоків, діагностичний експеримент способом генерації тестових патернів сигналів та аналіз результатів оброблення на виході системи. Досягнуті результати. На основі аналізу процедур взаємодії процесорного ядра та програмованої логіки на обраній платформі SoC спроєктовано модель системи оброблення сигналів аудіоспектра. Практичну реалізацію виконано на базі стеку інструментальних засобів САПР Vivado/Vitis/Vitis HLS. Проведено верифікацію запропонованої моделі з використанням програмованого генератора тестових сигналів та аналізу отриманих характеристик цифрових фільтрів на виході системи. Висновки. У статті проаналізовано принципи проєктування вбудованих систем оброблення інформації, що реалізуються в системах на кристалі. Розглянуто принципи побудови та аналізу систем цифрового оброблення сигналів на базі систем на кристалі, що містять програмовану логіку та процесорну частину. Розроблені методи апробовано на алгоритмах CIC- та FIR-фільтрів на технологічній платформі SoC FPGA сімейства ZYNQ-7000 фірми Xilinx

Effects of Fixed Point FFT Implementation of Wireless LAN

With the rapid growth of digital wireless communication in recent years, the need for high speed mobile data transmission has increased. New modulation techniques are being implemented to keep with the desire more communication capacity. Processing power has increased to a point where orthogonal frequency division multiplexing (OFDM) has become feasible and economical. Since many wireless communication systems being developed use OFDM, it is a worthwhile research topic. Some examples of applications using OFDM include Digital subscriber line (DSL), Digital Audio Broadcasting (DAB), High definition television (HDTV) broadcasting, IEEE 802.11 (wireless networking standard).OFDM is a strong candidate and has been suggested or standardized in high speed communication systems. This thesis analyzes the factor that affects the OFDM performance. The performance of OFDM was assessed by using computer simulations performed using Matlab.it was simulated under Additive white Gaussian noise (AWGN) channel conditions for different modulation schemes like binary phase shift keying (BPSK), Quadrature phase shift keying (QPSK), 16-Quadrature amplitude modulation (16-QAM), 64-Quadrature amplitude modulation (64-QAM) which are used in wireless LAN for achieving high data rates. One key component in OFDM based systems is inverse fast Fourier transform/fast Fourier transform (IFFT/FFT) computation, which performs the efficient modulation/demodulation. This block consumes large resources in terms of computational power.this thesis analyzes, different IFFT/FFT implementation on performance of OFDM communication system. Here 64-point IFFT/ FFT is used. FFT is a complex function whose computational accuracy, hardware size and processing speed depend on the type of arithmetic format used to implement it. Due to non-linearity of FFT its computational accuracy is not easy to calculate theoretically. The simulation carried out here, measure the effects of fixed point FFT on the performance of OFDM. Comparison has been made between bit error rate of OFDM using fixed point IFFT/FFT and a floating point IFFT/FFT. Simulation tests were made for different integer part lengths, fractional part lengths by limiting the input word lengths to 16 bits and found the suitable combination of integer part lengths and fractional part lengths which can achieve the best bit error rate (BER) performance with respect to floating point performance. Extensive computer simulations show that fixed point computation provides very near result as floating point if the delay parameter is suitably selected

Synthesis of a parallel data stream processor from data flow process networks

In this talk, we address the problem of synthesizing Process Network specifications to FPGA execution platforms. The process networks we consider are special cases of Kahn Process Networks. We call them COMPAAN Data Flow Process Networks (CDFPN) because they are provided by a translator called the COMPAAN compiler that automatically translates affine nested loop programs to input-output equivalent (COMPAAN) process network specifications. The objective is to provide an effective and efficient implementation of CDFPNs in an FPGA execution platform, where our implementation is close to a one-to-one mapping of the originating CDFPN. The execution platform emerges as part of the mapping process resulting in a dedicated multi-processor execution platform for a given CDFPN specification.LIACSUBL - phd migration 201

Proceedings of the 3rd International Workshop on Polyhedral Compilation Techniques

IMPACT 2013 in Berlin, Germany (in conjuction with HiPEAC 2013) is the third workshop in a series of international workshops on polyhedral compilation techniques. The previous workshops were held in Chamonix, France (2011) in conjuction with CGO 2011 and Paris, France (2012) in conjuction with HiPEAC 2012

Processing Systems EURASIP Journal on Embedded Systems Embedded Digital Signal Processing Systems

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Novel digital NGD Methodology for FPGA-based Embedded Systems

International audienceNegative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. NGD time-domain characterization was conducted using a sampling frequency of 1 MHz and Gaussian and sinc input signal waveforms. The calculated and experimental results are in excellent agreement, showing a desired time advance of 6 μ s and an average cross-correlation of 98%. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems