Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK

This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK® elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK® platform by using the MATLAB® engine library, so that the optimization core runs in background while MATLAB® acts as a computation engine. The implementation on the MATLAB® platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13)im CMOS 12bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.Ministerio de Ciencia y Tecnología TIC2003-02355RAICONI

Embedded processor system for controllable period-width multichannel pulse width modulation signals

This paper proposes a sophisticated embedded processor system configured on zynq-xc7z020 field programmable gate array (FPGA) device for generating four channels pulse width modulation signals with variable duty cycles and periods using embedded design techniques. The main advantages of the technique are the high ability to perform a simultaneous control on period and pulse width of the generated signals and a high system design adaptation to choose the number of input/output channels. Controlling the the period and the pulse width is achieved by injecting a digital signal to the designed system to manipulate embedded timers’ operation. Vivado design suite is used to develop the system hard ware in the integrated development environment where the processing unit and peripherals are instantiated and interconnected. A practical aplication program in C language is prepared to make the system act according to the target. The designed system can be used to drive multi-phase D.C to D.C convertors. The system performance is verified by using vivado logic analyzer and chipscope windows. The superiority of the proposed approach over other approaches is that it resulted in a multi-inputs/multi-outputs pulse width modulation system with high controllability on the pulse width and the period that ranges from 15 nsec to 60 sec

Feldspar: Application and Implementation

The Feldspar project aims to develop a domain specific language for Digital Signal Processing algorithm design. From functional descriptions, imperative code (currently C) is generated. The project partners are Ericsson, Chalmers and ELTE, Budapest. The background and motivation for the project have been documented elsewhere [3]. We aim to raise the level of abstraction at which algorithm developers and implementors work, and to generate, from Feldspar descriptions, the kind of code that is currently written by hand. These lecture notes first give a brief introduction to Feldspar and the style of programming that it encourages. Next, we document the implementation of Feldspar as a domain specific language (DSL), embedded in Haskell. The implementation is built using a library called Syntactic that was built for this purpose, but also designed to be of use to other implementors of embedded domain specific languages. We show the implementation of Feldspar in sufficient detail to give the reader an understanding of how the use of the Syntactic library enables the modular construction of an embedded DSL. For those readers who would like to apply these techniques to their own DSL embedded in Haskell, further instructions are given in section 5. The programming examples are available in the CEFP directory of the Feldspar package, version 0.5.0.1: http://hackage.haskell.org/package/ feldspar-language-0.5.0.1 The code can be fetched by running: > cabal unpack feldspar-language-0.5.0.1 All code is written in Haskell, and has been tested using the Glasgow Haskell Compiler (GHC), version 7.0.2, and the packages syntactic-0.8 feldspar-language-0.5.0.1 feldspar-compiler-0.5.0.

Voltage-to-Frequency Converter for Low-Power Sensor Interfaces

This work presents a low-power rail-to-rail temperature compensated voltage-to-frequency converter (VFC) which constitutes the last stage of a sensor read-out interface targeting wireless sensor networks (WSN) applications. These quasi-digital converters are now receiving great interest, since they combine the simplicity of analog devices with the accuracy and noise immunity proper to digital signal processing; besides, frequency output is directly driven to the embedded node microcontroller C, which next performs the A/D conversion using its internal timers. A first read-out interface prototype using low-voltage low-power commercial components shows that the VFC means 99 % of the total interface consumption in read-out mode. Further, existing CMOS VFCs in the form of ASICs have a rather limited input range and an unsuitable output frequency span for typical C clock frequencies used in WSN. Hence, a novel full custom VFC solution is needed, fullfilling the main requirements of rail-to-rail operation, to take advantage of the full supply voltage range to optimize the output frequency resolution, and low-power low-voltage operation to have a power supply compatible with conventional WSN batteries while maximizing the operating life of the sensor node. Experimental results for a 0.18–μm 1.2–V CMOS VFC implementation show for an input range of (0–1.2 V) an output frequency range of (0.1–1.0 MHz), adequate to digitize the signal with the direct counting method in the sensor node μC achieving 13 bits resolution. It has a power consumption of 60 μW (35 nW in sleep mode) and it is temperature insensitive for a temperature range of (-40, 120 ºC)

Perceptual Copyright Protection Using Multiresolution Wavelet-Based Watermarking And Fuzzy Logic

In this paper, an efficiently DWT-based watermarking technique is proposed to embed signatures in images to attest the owner identification and discourage the unauthorized copying. This paper deals with a fuzzy inference filter to choose the larger entropy of coefficients to embed watermarks. Unlike most previous watermarking frameworks which embedded watermarks in the larger coefficients of inner coarser subbands, the proposed technique is based on utilizing a context model and fuzzy inference filter by embedding watermarks in the larger-entropy coefficients of coarser DWT subbands. The proposed approaches allow us to embed adaptive casting degree of watermarks for transparency and robustness to the general image-processing attacks such as smoothing, sharpening, and JPEG compression. The approach has no need the original host image to extract watermarks. Our schemes have been shown to provide very good results in both image transparency and robustness.Comment: 13 pages, 7 figure