Double-Layer No-Flow Underfill Process for Flip-Chip Applications

©2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.No-flow underfill technology shows potential advances over the conventional underfill technology toward a low-cost flop-chip underfill process. However, due to the filler entrapment in between solder bumps and contact pads on board, no-flow underfills are mostly unfilled or filled with very low filler loading. The high coefficient of thermal expansion (CTE) of the polymer material has significantly lowered the reliability of flip chip assembly and has limited its application to large chip assemblies. This paper presents a double-layer no-flow underfill process approach to incorporate silica filler into a no-flow underfill. Two layers of underfills are applied on to the substrate before chip placement. The bottom underfill layer facing the substrate is fluxed and unfilled; the upper layer facing the chip is filled with silica fillers. The total filler loading of the mixture is estimated to be around 55 wt%. The material properties of each layer of underfills, the underfill mixture, and a control unfilled underfill are characterized using differential scanning calorimeter (DCS), thermo-mechanical analyzer (TMA), dynamic mechanical analyzer (DMA), and a stress rheometer. FB250 daisy-chained test chips are assembled on FR-4 boards using the novel approach. A 100% assembly yield of solder Interconnect is achieved with the double-layer no-flow underfill while in the single-layer no-flow underfill process, no solder joint yield is observed. Scanning electronic microscope (SEM) and optical microscope are used to investigate the cross-section of both assemblies. A US provisional patent has been filed for this invention

Time-resolved high-harmonic spectroscopy of ultrafast photo-isomerization dynamics

We report the first study of time-resolved high-harmonic spectroscopy (TR-HHS) of a bond-making chemical reaction. We investigate the transient change of the high harmonic signal from 1,3-cyclohexadiene (CHD), which undergoes ring-opening and isomerizes to 1,3,5-hexatriene (HT) upon photoexcitation. By associating the change of the harmonic yield with the changes of the ionization energy and vibrational frequency of the molecule due to the isomerization, we find that the electronic excited state of CHD created via two-photon absorption of 3.1 eV photons relaxes almost completely within 80 fs to the electronic ground state of CHD with vibrational excitation. Subsequently, the molecule isomerizes abruptly to HT, i.e., ring-opening occurs, around 400 fs after the excitation. The present results demonstrate that TR-HHS, which can track both the electronic and the nuclear dynamics, is a powerful tool for unveiling ultrafast photo-chemical reactions.Comment: 25 pages, 7 figure

Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them