MISSED: an environment for mixed-signal microsystem testing and diagnosis

A tight link between design and test data is proposed for speeding up test-pattern generation and diagnosis during mixed-signal prototype verification. Test requirements are already incorporated at the behavioral level and specified with increased detail at lower hierarchical levels. A strict distinction between generic routines and implementation data makes reuse of software possible. A testability-analysis tool and test and DFT libraries support the designer to guarantee testability. Hierarchical backtrace procedures in combination with an expert system and fault libraries assist the designer during mixed-signal chip debuggin

RON-BEAM DEBUG AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS

A current research project at IMAG/TIM3 Laboratory aims at an integrated test system combining the use of the Scanning Electron Microscope (SEM), used in voltage contrast mode, with a new high-level approach of fault location in complex VLSI circuits, in order to reach a complete automated diagnosis process. Two research themes are induced by this project, which are: prototype validation of known circuits, on which CAD information is available, and failure analysis of unknown circuits, which are compared to reference circuits. For prototype validation, a knowledge-based approach to fault location is used. Concerning failure analysis, automatic image comparison based on pattern recog- nition techniques is performed. The purpose of the paper is to present these two methodologies, focusing on the SEM-based data acquisition process

Test methodologies of VLSI circuits using scanning electron microscope.

by Chan Lap-kong.Thesis (M.Phil.)--Chinese University of Hong Kong, 1994.Includes bibliographical references (leaves 77-80).ABSTRACTACKNOWLEDGEMENTSLIST OF FIGURESChapter 1. --- INTRODUCTION --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Problems in Testing VLSI Circuits --- p.3Chapter 1.2.1 --- Test-cost-per-gate --- p.3Chapter 1.2.2 --- Tester Complexity --- p.3Chapter 1.3 --- Tester Based on Terminals Characteristics -Automatic Testing Equipment(ATE) --- p.4Chapter 1.4 --- Tester Based on Terminal and Internal Characteristics --- p.6Chapter 1.4.1 --- Mechanical Probing Method --- p.6Chapter 1.4.2 --- E-beam Probing Method --- p.7Chapter 1.5 --- Movitation for this Research --- p.7Chapter 1.6 --- Outline of the Remaining Chapters --- p.9Chapter 2. --- E-BEAM TESTER --- p.10Chapter 2.1 --- State-of-art of E-Beam Tester --- p.10Chapter 2.2 --- An Electron-optical Column of a SEM --- p.12Chapter 2.3 --- Beam Rastering Methods --- p.13Chapter 2.4 --- Voltage Contrast Phenomenon --- p.14Chapter 2.5 --- Configuration of an E-Beam Test System --- p.18Chapter 2.6 --- Advantages of an E-beam Tester --- p.20Chapter 3. --- BASIC PRINCIPLES --- p.21Chapter 3.1 --- Single-Stuck-At Fault Model --- p.21Chapter 3.2 --- Observability and Controllability --- p.24Chapter 3.3 --- Netlist Format --- p.25Chapter 3.4 --- Level --- p.27Chapter 3.5 --- Reconvergent Fanout --- p.28Chapter 4. --- CONVENTIONAL TEST GENERATION --- p.29Chapter 4.1 --- Conventional Automatic Test Generation for ATEs --- p.29Chapter 4.3 --- Conventional E-Beam Test Generation --- p.31Chapter 5. --- TEST AND PROBE POINT GENERATION --- p.32Chapter 5.1 --- Wafer Stage E-beam Testing --- p.32Chapter 5.2 --- Critical Paths Generation --- p.33Chapter 5.3 --- Assumptions of the Test and Probe Point Generation Algorithm --- p.35Chapter 5.4 --- Rules of the Test and Probe Point Generation Algorithm --- p.36Chapter 5.5 --- Probe Points Selection and Reduction --- p.38Chapter 5.6 --- Test and Probe Point Generation Algorithm --- p.40Chapter 5.7 --- Propagation and Justification at Fanout Site --- p.42Chapter 6. --- EXAMPLES --- p.45Chapter 6.1 --- Example of Test and Probe Point Generation for Circuit sc2 --- p.45Chapter 6.2 --- Example of Test and Probe Point Generation for Circuit sfc4 --- p.53Chapter 7. --- CONCLUSIONS --- p.61Chapter 7.1 --- Summary of Results --- p.61Chapter 7.2 --- Further Research --- p.63APPENDIXAppendix A: Algorithm to Find Reconvergent FanoutsAppendix B: Results of Test Generation for Circuit sc1Appendix C: Results of Test Generation for Circuit sc3REFERENCES --- p.7

High Speed Test Interface Module Using MEMS Technology

With the transient frequency of available CMOS technologies exceeding hundreds of gigahertz and the increasing complexity of Integrated Circuit (IC) designs, it is now apparent that the architecture of current testers needs to be greatly improved to keep up with the formidable challenges ahead. Test requirements for modern integrated circuits are becoming more stringent, complex and costly. These requirements include an increasing number of test channels, higher test-speeds and enhanced measurement accuracy and resolution. In a conventional test configuration, the signal path from Automatic Test Equipment (ATE) to the Device-Under-Test (DUT) includes long traces of wires. At frequencies above a few gigahertz, testing integrated circuits becomes a challenging task. The effects on transmission lines become critical requiring impedance matching to minimize signal reflection. AC resistance due to the skin effect and electromagnetic coupling caused by radiation can also become important factors affecting the test results. In the design of a Device Interface Board (DIB), the greater the physical separation of the DUT and the ATE pin electronics, the greater the distortion and signal degradation. In this work, a new Test Interface Module (TIM) based on MEMS technology is proposed to reduce the distance between the tester and device-under-test by orders of magnitude. The proposed solution increases the bandwidth of test channels and reduces the undesired effects of transmission lines on the test results. The MEMS test interface includes a fixed socket and a removable socket. The removable socket incorporates MEMS contact springs to provide temporary with the DUT pads and the fixed socket contains a bed of micro-pins to establish electrical connections with the ATE pin electronics. The MEMS based contact springs have been modified to implement a high-density wafer level test probes for Through Silicon Vias (TSVs) in three dimensional integrated circuits (3D-IC). Prototypes have been fabricated using Silicon On Insulator SOI wafer. Experimental results indicate that the proposed architectures can operate up to 50 GHz without much loss or distortion. The MEMS probes can also maintain a good elastic performance without any damage or deformation in the test phase

Single event phenomena: Testing and prediction

Highly integrated microelectronic devices are often used to increase the performance of satellite systems while reducing the system power dissipation, size, and weight. However, these devices are usually more susceptible to radiation than less integrated devices. In particular, the problem of sensitivity to single event upset and latchup is greatly increased as the integration level is increased. Therefore, a method for accurately evaluating the susceptibility of new devices to single event phenomena is critical to qualifying new components for use in space systems. This evaluation includes testing devices for upset or latchup and extrapolating the results of these tests to the orbital environment. Current methods for testing devices for single event effects are reviewed, and methods for upset rate prediction, including a new technique based on Monte Carlo simulation, are presented