Atomic layer deposition of binary and ternary lead and bismuth oxide thin films

This thesis describes the deposition of binary lead oxide and ternary lead titanate, lead zirconate, bismuth silicate, and bismuth titanate films by atomic layer deposition (ALD) and characterization of structural, compositional and surface properties of the films. The first part of the thesis reviews the principles of the ALD technique and the relevant literature on perovskite oxides and films and the deposition of lead and bismuth films by ALD, and the second part summarizes the experimental work reported in the five appended publications. On the basis of the binary lead oxide depositions, the Ph4Pb/O3 process was chosen for the ternary oxide studies. Careful optimization of the pulsing ratio of the binary oxides allowed processing of stoichiometric perovskite PbTiO3 and PbZrO3 thin films. Crystalline PbTiO3 on Si(100) was detected after annealing at 600 °C. In the case of lead zirconate, the perovskite phase (PbZrO3) was obtained on SrTiO3(100) after annealing at 600 °C. In both cases, a slight excess of lead enhanced the crystallinity. Roughness values were nevertheless higher than values obtained in binary processes. A new bimetallic precursor Bi(CH2SiMe3)3 was introduced for the deposition of bismuth silicate. With ozone as oxidizing agent, ALD-window for Bi-Si-O thin film growth was found at 250-350 °C. The Si to Bi atomic ratio in this region was about 2. Addition of a second bismuth precursor, BiPh3, increased the bismuth content. Combination of the BiPh3/O3 process and the Ti(O-i-Pr)4/H2O process allowed successful deposition of bismuth titanate. Good control of the film stoichiometry was achieved at the deposition temperature of 250 °C. Both as-deposited ternary bismuth oxides were amorphous. After annealing at 600 °C, the a-axis-oriented Bi2SiO5 phase was detected. Higher annealing temperatures were necessary for bismuth titanate. The most textured film of Bi4Ti3O12 was obtained in N2 atmosphere at annealing temperature of 1000 °C. Roughness values of the thin films were reasonable, being in the range of 0.3-1.3 nm.reviewe

Solution-Processed Metal Oxide Gate Dielectrics and Their Implementations in Zinc Oxide Based Thin Film Transistors

Thin-film transistors (TFTs) based on oxide semiconductors are a promising technology for a host of large-volume electronic applications. Whilst progress on solution-processed oxide semiconductors has been rapidly advancing, research efforts towards the development of new dielectrics has been relatively slow, with most of the reported work performed using conventional dielectrics based in SiO2. As a result, the majority of oxide transistors reported to date operate at relatively high voltages and hence consume significantly more power. In order to circumvent this bottleneck, recent work has been focussing on the development of low-voltage oxide transistors, including the use of high-k dielectrics, and several candidates have already been investigated and were mostly deposited by costly vacuum-based techniques. This thesis investigates the properties of high-k metal oxides dielectrics as well as their implementation in TFTs, deposited by spray pyrolysis, a simple and versatile technique that combines high yield and large area compatibility. In particular, the structural, optical, surface and electronic properties of tantalum aluminate (TaAlOx), hafnium titanate (HfTiO4) and zirconium silicate (ZrSiO4) were studied as along with their performance as gate dielectric for TFTs implementing ZnO semiconducting channels. In all cases, stochiometric TaAlOx, HfTiO4 and ZrSiO4 films deposited at < 550 °C were found to be amorphous with surface roughness of < 1 nm. The optical bandgap varies between 4.9 eV and 8.8 eV, 5.8 eV and 3.8 eV, and 5.8 eV and 8 eV for TaAlOx, HfTiO4 and ZrSiO4 films respectively. Their dielectric constant values vary between 24 and 7, 14 and 60, and 23 and 4.2 while their leakage current density at 1 MV/cm were between 10^-6 A/cm^2 and 10^-10 A/cm^2, 10^-7 A/cm^2 and 10 A/cm^2, and 10^-5 A/cm^2 and 10^-4 A/cm^2 respectively. Particularly, the stoichiometric TaAlOx, HfTiO4 and ZrSiO4 films exhibited the bandgap of 5.4 eV, 4.4 eV, 6.1 eV, dielectric constant of 13, 30, 12 and leakage current density at 1 MV/cm of 10^-8 A/cm^2, 0.3 A/cm^2, 10^-7 A/cm^2 respectively. The performance of ZnO – based TFTs employing stoichiometric TaAlOx, HfTiO4 and ZrSiO4 gate dielectric showed promising characteristics such as low voltage operation of 4 V, high electron mobility of 16 cm^2/Vs, 7 cm^2/Vs, 57 cm^2/Vs, high current modulation ratio of 10^5, 10^7, 10^6, low subthreshold swing of 0.56 V/dec, 0.17 V/dec, 0.28 V/dec, interface trap density of 7.7x10^12 cm^-2 ,2.1x10^12 cm^-2, 10^13 cm^-2 and threshold voltage of 3.2V, 0.6V, 0.1 V respectively. In addition, the effect of post-deposition annealing (at 800 °C for 30 mins in air) on HfTiO4 films were investigated. Stochiometric HfTiO4 films were crystalline of an orthorhombic structure, surface roughness of 1.95 nm, optical bandgap of 4.36 eV, dielectric constant of 38 and leakage current density of 5 mA/cm^2 at 1 MV/cm. These remarkable findings significantly demonstrated the achievement of a high- performance high-k metal oxide gate dielectrics as alternatives to the conventional SiO2 for future integration into wide areas of electronic application

Dielectric relaxation and frequency dependence of Hf02 doped by lanthanide elements

The decreasing sizes in complementary metal oxide semiconductor (CMOS) transistor technology requires the replacement of SiO2 with gate dielectrics that have a high dielectric constant (k). When the SiO2 gate thickness was reduced below 1.4 nm, electron tunneling effects and high leakage currents occurred which presented serious obstacles for the reliability issue in terms of metal-oxide-semiconductor field-effect transistor (MOSFET) devices. In recent years, various alternative gate dielectrics have been researched. Following the introduction of HfO2 into the 45 nm process by Intel in 2007, the screening and selection of high-k gate stacks, understanding their properties, and their integration into CMOS technology has been a very active research area. Frequency dispersion of high-k dielectrics was commonly observed and classified into two parts: extrinsic and intrinsic causes. The frequency dependence of the dielectric constant (k-value), that is the intrinsic frequency dispersion, could not be assessed before suppressing the effects of extrinsic frequency dispersion, such as the effects of the lossy interfacial layer (between the high-k thin film and silicon substrate) and the parasitic effects. The significance of parasitic effects (including series resistance and the back metal contact of the metal-oxide-semiconductor (MOS) capacitor) on frequency dispersion was studied. The effect of the lossy interfacial layer on frequency dispersion was investigated and modeled using a dual frequency technique. The effect of surface roughness on frequency dispersion is also investigated. Several mathematical models were discussed to describe the dielectric relaxation of high-k dielectrics. Some of the relaxation behavior can be modeled using the Curie-von Schweidler (CS) law, the Kohlrausch-Williams-Watts (KWW) relationship and the Havriliak-Negami (HN) relationship. Other relaxation models were also introduced. For the physical mechanism, dielectric relaxation was found to be related to the degree of polarization, which was dependent on the structure of the high-k material. The degree of polarization was attributed to the enhancement of the correlations among polar nano-scale size domain within the materials. The effect of grain size for the high-k materials' structure mainly originated from higher surface stress in smaller grain size due to its higher concentration of grain boundary

Rare Earth Silicate Formation: A Route Towards High-k for the 22 nm Node and Beyond, Journal of Telecommunications and Information Technology, 2009, nr 4

Over the last decade there has been a significant amount of research dedicated to finding a suitable high-k/metal gate stack to replace conventional SiON/poly-Si electrodes. Materials innovations and dedicated engineering work has enabled the transition from research lab to 300 mm production a reality, thereby making high-k/metal gate technology a pathway for continued transistor scaling. In this paper, we will present current status and trends in rare earthbased materials innovations; in particular Gd-based, for the high-k/metal gate technology in the 22 nm node. Key issues and challenges for the 22 nm node and beyond are also highlighted

Direct liquid injection chemical vapor deposition of ZrO2 films from a heteroleptic Zr precursor: Interplay between film characteristics and corrosion protection of stainless steel

The direct liquid injection chemical vapor deposition (DLI-CVD) of uniform and dense zirconium oxide (ZrO2) thin films applicable as corrosion protection coatings (CPCs) is reported. We present the entire development chain from the rational choice and thermal evaluation of the suitable heteroleptic precursor [Zr(OiPr)2(tbaoac)2] over the detailed DLI-CVD process design and finally benchmarking the CPC behavior using electrochemical impedance spectroscopy (EIS). For a thorough development of the growth process, the deposition temperature (Tdep) is varied in the range of 400 – 700 °C on Si(100) and stainless steel (AISI 304) substrates. Resulting thin films are thoroughly analyzed in terms of structure, composition, and morphology. Grazing incidence X-ray diffractometry (GIXRD) reveals an onset of crystallization at Tdep ≥ 500 °C yielding monoclinic and even cubic phase at low temperatures. At Tdep = 400 °C, isotropic growth of XRD amorphous material is shown to feature cubic crystalline domains at the interfacial region as revealed by electron diffraction. Corrosion results obtained through EIS measurements and further immersion tests revealed improved CPC characteristic for the 400 °C processed ZrO2 coatings compared to the ones deposited at Tdep ≥ 500 °C, yielding valuable insights into the correlation between growth parameter and CPC performance which are of high relevance for future exploration of CPCs

Review and perspective of high-k dielectrics on silicon, Journal of Telecommunications and Information Technology, 2007, nr 2

The paper reviews recent work in the area of high-k dielectrics for application as the gate oxide in advanced MOSFETs. Following a review of relevant dielectric physics, we discuss challenges and issues relating to characterization of the dielectrics, which are compounded by electron trapping phenomena in the microsecond regime. Nearly all practical methods of preparation result in a thin interfacial layer generally of the form SiOx or a mixed oxide between Si and the high-k so that the extraction of the dielectric constant is complicated and values must be qualified by error analysis. The discussion is initially focussed on HfO2 but recognizing the propensity for crystallization of that material at modest temperatures, we discuss and review also, hafnia silicates and aluminates which have the potential for integration into a full CMOS process. The paper is concluded with a perspective on material contenders for the “end of road map” at the 22 nm node

High-k gadolinium scandate on Si obtained by high pressure sputtering from metal targets and in-situ plasma oxidation

This article studies the physical and electrical behavior of Gd2-xScxO3 layers grown by high pressure sputtering from metallic Gd and Sc targets. The aim is to obtain a high permittivity dielectric for microelectronic applications. The films were obtained by the deposition of a metallic nanolaminate of Gd and Sc alternating layers, which is afterwards in-situ oxidized by plasma. The oxide films obtained were close to stoichiometry, amorphous and with minimal interfacial regrowth. By fabricating metal-insulator-semiconductor capacitors we found that a moderate temperature annealing is needed to enhance permittivity, which reaches a high value of 32 while keeping moderate leakage. Finally, the feasibility of interface scavenging in this material with Ti gate electrodes is also demonstrated.Comment: 36 pages, 13 figure