ON ACCELERATION OF THERMAL SIMULATION OF URBAN SCENES WITH THE APPLICATION OF AN EVOLUTIONARY ALGORITHM TO TREE PLANTING STRATEGIES

Tree planting is one of the most popular in urban morphology measures for urban heat island reduction since, at a relatively low monetary cost and with a marginal alteration of the scene, trees provide shadows and neutralize harmful gases. Findings for their optimal distribution within the urban scene exist in numerous environmental studies. However, merely the digital twin of the scene possesses the capability to analyze further developments of the scene, such as changes in dominant wind directions. Today’s extensive computational resources allow for thermal simulations of digital twins on multiple (not-yet-existing) urban scene designs, aiming at minimizing the average or peak temperatures. From the point of view of computer graphics, this paper proposes four tools to accelerate an evolutionary algorithm for tree planting strategies. Using GPU arrays for rendering, pre-rendering default scenes, and pre-filtering trees in the early morning and late evening hours helps accelerating the rendering process. Computation of fitness function on different computers allows a further acceleration of the evolutionary algorithm. The total acceleration factor of a scene using computational set-up exceeds 218, thus demonstrating the enormous potential the evolutionary algorithm may bring about in future investigations

Dynamic acceleration structures for the visualization of time-dependent volume data on the GPU

Volume rendering extensive 3D data is requiring much computing power and doing this efficiently has been a challenge. To build a data structure of which rendering can take advantage is a common solution. Among others these data structures are built with the purpose of empty space skipping and adaptive sampling. Empty space skipping is the main strategy of acceleration in this work. Octree and Kd-tree is constructed and analyzed in reference to construction and rendering performance. Time-dependent data often come from numerical simulation and show similarities between two successive time instances. These similarities can be exploited to facilitate construction. The method and consequences of this exploitation will be discussed. Naive volume rendering is conceptually suitable for parallel computing. On the other side, both constructing and traversal of hiearchical data structures do not seem to agree with parallel nature of GPUs. Still implementation techniques to bypass GPU-specific traps of performance is applied in order to utilize the enormous computing power of GPUs

Lichttransportsimulation auf Spezialhardware

It cannot be denied that the developments in computer hardware and in computer algorithms strongly influence each other, with new instructions added to help with video processing, encryption, and in many other areas. At the same time, the current cap on single threaded performance and wide availability of multi-threaded processors has increased the focus on parallel algorithms. Both influences are extremely prominent in computer graphics, where the gaming and movie industries always strive for the best possible performance on the current, as well as future, hardware. In this thesis we examine the hardware-algorithm synergies in the context of ray tracing and Monte-Carlo algorithms. First, we focus on the very basic element of all such algorithms - the casting of rays through a scene, and propose a dedicated hardware unit to accelerate this common operation. Then, we examine existing and novel implementations of many Monte-Carlo rendering algorithms on massively parallel hardware, as full hardware utilization is essential for peak performance. Lastly, we present an algorithm for tackling complex interreflections of glossy materials, which is designed to utilize both powerful processing units present in almost all current computers: the Centeral Processing Unit (CPU) and the Graphics Processing Unit (GPU). These three pieces combined show that it is always important to look at hardware-algorithm mapping on all levels of abstraction: instruction, processor, and machine.Zweifelsohne beeinflussen sich Computerhardware und Computeralgorithmen gegenseitig in ihrer Entwicklung: Prozessoren bekommen neue Instruktionen, um zum Beispiel Videoverarbeitung, Verschlüsselung oder andere Anwendungen zu beschleunigen. Gleichzeitig verstärkt sich der Fokus auf parallele Algorithmen, bedingt durch die limitierte Leistung von für einzelne Threads und die inzwischen breite Verfügbarkeit von multi-threaded Prozessoren. Beide Einflüsse sind im Grafikbereich besonders stark , wo es z.B. für die Spiele- und Filmindustrie wichtig ist, die bestmögliche Leistung zu erreichen, sowohl auf derzeitiger und zukünftiger Hardware. In Rahmen dieser Arbeit untersuchen wir die Synergie von Hardware und Algorithmen anhand von Ray-Tracing- und Monte-Carlo-Algorithmen. Zuerst betrachten wir einen grundlegenden Hardware-Bausteins für alle diese Algorithmen, die Strahlenverfolgung in einer Szene, und präsentieren eine spezielle Hardware-Einheit zur deren Beschleunigung. Anschließend untersuchen wir existierende und neue Implementierungen verschiedener MonteCarlo-Algorithmen auf massiv-paralleler Hardware, wobei die maximale Auslastung der Hardware im Fokus steht. Abschließend stellen wir dann einen Algorithmus zur Berechnung von komplexen Beleuchtungseffekten bei glänzenden Materialien vor, der versucht, die heute fast überall vorhandene Kombination aus Hauptprozessor (CPU) und Grafikprozessor (GPU) optimal auszunutzen. Zusammen zeigen diese drei Aspekte der Arbeit, wie wichtig es ist, Hardware und Algorithmen auf allen Ebenen gleichzeitig zu betrachten: Auf den Ebenen einzelner Instruktionen, eines Prozessors bzw. eines gesamten Systems

Doctor of Philosophy in Computer Science

dissertationRay tracing is becoming more widely adopted in offline rendering systems due to its natural support for high quality lighting. Since quality is also a concern in most real time systems, we believe ray tracing would be a welcome change in the real time world, but is avoided due to insufficient performance. Since power consumption is one of the primary factors limiting the increase of processor performance, it must be addressed as a foremost concern in any future ray tracing system designs. This will require cooperating advances in both algorithms and architecture. In this dissertation I study ray tracing system designs from a data movement perspective, targeting the various memory resources that are the primary consumer of power on a modern processor. The result is high performance, low energy ray tracing architectures

BRDF Editor

Název: BRDF Editor Autor: Jan Waltl Katedra: Katedra softwaru a výuky informatiky Vedoucí práce: RNDr. Josef Pelikán, Katedra softwaru a výuky informatiky Abstrakt: Cílem této práce je vytvořit prostředí pro tvorbu a editaci materiálů v podobě bidirectional reflectance functions(BRDF) (obousměrné distribuční funkce odrazu světla). Výsledkem práce je grafická aplikace umožňující psaní těchto funkcí, náhled jejich chování ve formě 2D grafů a otestování v jednoduchých prostředích. Aby se toho dosáhlo, bude část programu využívat grafické karty skrze OpenCL. Tento přístup by měl umožnit interaktivní práci s funkcemi. Součástí je imple- mentace známých algoritmů sledování paprsků, které právě dokáží vykreslovat realisticky vypadající obrázky včetně nepřímého osvětlení. Tyto algoritmy budou používat metodu vzorkování dle důležitosti, včetně možnosti napsaní vlastního vzorkování pro dané BRDF. Klíčová slova: BRDF OpenCL photo-realistic rendering path tracing GPU iiiTitle: BRDF Editor Author: Jan Waltl Department: Department of Software and Computer Science Education Supervisor: RNDr. Josef Pelik'an, Department of Software and Computer Science Education Abstract: The goal of this thesis is to create a working environment for the development and testing of bidirectional reflectance functions (BRDFs). The result of our work is a graphical application that offers tools to write these BRDFs, see how they behave on dynamic 2D graphs and in simple scenes. To achieve this, we created a general framework for physically based rendering algorithms. With the help of accelerating in hardware, in particular graphics cards(GPUs), we use OpenCL API to boost performance and allow interactive work with the developed functions. As part of the work, we implemented the path tracing algorithm capable of rendering realistic-looking scenes with indirect lighting from area lights and an environment light. The used algorithm uses importance sampling to greatly improve convergence speed and allows writing these custom sampling strategies for the written BRDFs and seeing how they match the BRDF, thus testing their effectiveness. Keywords: BRDF OpenCL photo-realistic rendering path tracing GPU iiiKatedra softwaru a výuky informatikyDepartment of Software and Computer Science EducationFaculty of Mathematics and PhysicsMatematicko-fyzikální fakult

Hardware Accelerators for Animated Ray Tracing

Future graphics processors are likely to incorporate hardware accelerators for real-time ray tracing, in order to render increasingly complex lighting effects in interactive applications. However, ray tracing poses difficulties when drawing scenes with dynamic content, such as animated characters and objects. In dynamic scenes, the spatial datastructures used to accelerate ray tracing are invalidated on each animation frame, and need to be rapidly updated. Tree update is a complex subtask in its own right, and becomes highly expensive in complex scenes. Both ray tracing and tree update are highly memory-intensive tasks, and rendering systems are increasingly bandwidth-limited, so research on accelerator hardware has focused on architectural techniques to optimize away off-chip memory traffic. Dynamic scene support is further complicated by the recent introduction of compressed trees, which use low-precision numbers for storage and computation. Such compression reduces both the arithmetic and memory bandwidth cost of ray tracing, but adds to the complexity of tree update.This thesis proposes methods to cope with dynamic scenes in hardware-accelerated ray tracing, with focus on reducing traffic to external memory. Firstly, a hardware architecture is designed for linear bounding volume hierarchy construction, an algorithm which is a basic building block in most state-of-the-art software tree builders. The algorithm is rearranged into a streaming form which reduces traffic to one-third of software implementations of the same algorithm. Secondly, an algorithm is proposed for compressing bounding volume hierarchies in a streaming manner as they are output from a hardware builder, instead of performing compression as a postprocessing pass. As a result, with the proposed method, compression reduces the overall cost of tree update rather than increasing it. The last main contribution of this thesis is an evaluation of shallow bounding volume hierarchies, common in software ray tracing, for use in hardware pipelines. These are found to be more energy-efficient than binary hierarchies. The results in this thesis both confirm that dynamic scene support may become a bottleneck in real time ray tracing, and add to the state of the art on tree update in terms of energy-efficiency, as well as the complexity of scenes that can be handled in real time on resource-constrained platforms