Interconnect capacitance extraction under geometric uncertainties

Interconnects are an important constituent of any large scale integrated circuit, and accurate interconnect analysis is essential not only for post-layout verification but also for synthesis. For instance, extraction of interconnect capacitance is needed for the prediction of interconnect-induced delay, crosstalk, and other signal distortion related effects that are used to guide IC routing and floor planning. The continuous progress of semiconductor technology is leading ICs to the era of 45 nm technology and beyond. However, this progress has been associated with increasing variability during the manufacturing processes. This variability leads to stochastic variations in geometric and material parameters and has a significant impact on interconnect capacitance. It is therefore important to be able to quantify the effect of such process induced variations on interconnect capacitance. In this thesis, we have worked on a methodology towards modeling of interconnect capacitance in the presence of geometric uncertainties. More specifically, a methodology is proposed for the finite element solution of Laplace's equation for the calculation of the per-unit-length capacitance matrix of a multi-conductor interconnect structure embedded in a multi-layered insulating substrate and in the presence of statistical variation in conductor and substrate geometry. The proposed method is founded on the idea of defining a single, mean geometry, which is subsequently used with a single finite element discretization, to extract the statistics of the interconnect capacitance in an expedient fashion. We demonstrate the accuracy and efficiency of our method through its application to the extraction of capacitances in some representative geometries for IC interconnects

Integrated Circuits Parasitic Capacitance Extraction Using Machine Learning and its Application to Layout Optimization

The impact of parasitic elements on the overall circuit performance keeps increasing from one technology generation to the next. In advanced process nodes, the parasitic effects dominate the overall circuit performance. As a result, the accuracy requirements of parasitic extraction processes significantly increased, especially for parasitic capacitance extraction. Existing parasitic capacitance extraction tools face many challenges to cope with such new accuracy requirements that are set by semiconductor foundries (\u3c 5% error). Although field-solver methods can meet such requirements, they are very slow and have a limited capacity. The other alternative is the rule-based parasitic capacitance extraction methods, which are faster and have a high capacity; however, they cannot consistently provide good accuracy as they use a pre-characterized library of capacitance formulas that cover a limited number of layout patterns. On the other hand, the new parasitic extraction accuracy requirements also added more challenges on existing parasitic-aware routing optimization methods, where simplified parasitic models are used to optimize layouts. This dissertation provides new solutions for interconnect parasitic capacitance extraction and parasitic-aware routing optimization methodologies in order to cope with the new accuracy requirements of advanced process nodes as follows. First, machine learning compact models are developed in rule-based extractors to predict parasitic capacitances of cross-section layout patterns efficiently. The developed models mitigate the problems of the pre-characterized library approach, where each compact model is designed to extract parasitic capacitances of cross-sections of arbitrary distributed metal polygons that belong to a specific set of metal layers (i.e., layer combination) efficiently. Therefore, the number of covered layout patterns significantly increased. Second, machine learning compact models are developed to predict parasitic capacitances of middle-end-of-line (MEOL) layers around FINFETs and MOSFETs. Each compact model extracts parasitic capacitances of 3D MEOL patterns of a specific device type regardless of its metal polygons distribution. Therefore, the developed MEOL models can replace field-solvers in extracting MEOL patterns. Third, a novel accuracy-based hybrid parasitic capacitance extraction method is developed. The proposed hybrid flow divides a layout into windows and extracts the parasitic capacitances of each window using one of three parasitic capacitance extraction methods that include: 1) rule-based; 2) novel deep-neural-networks-based; and 3) field-solver methods. This hybrid methodology uses neural-networks classifiers to determine an appropriate extraction method for each window. Moreover, as an intermediate parasitic capacitance extraction method between rule-based and field-solver methods, a novel deep-neural-networks-based extraction method is developed. This intermediate level of accuracy and speed is needed since using only rule-based and field-solver methods (for hybrid extraction) results in using field-solver most of the time for any required high accuracy extraction. Eventually, a parasitic-aware layout routing optimization and analysis methodology is implemented based on an incremental parasitic extraction and a fast optimization methodology. Unlike existing flows that do not provide a mechanism to analyze the impact of modifying layout geometries on a circuit performance, the proposed methodology provides novel sensitivity circuit models to analyze the integrity of signals in layout routes. Such circuit models are based on an accurate matrix circuit representation, a cost function, and an accurate parasitic sensitivity extraction. The circuit models identify critical parasitic elements along with the corresponding layout geometries in a certain route, where they measure the sensitivity of a route’s performance to corresponding layout geometries very fast. Moreover, the proposed methodology uses a nonlinear programming technique to optimize problematic routes with pre-determined degrees of freedom using the proposed circuit models. Furthermore, it uses a novel incremental parasitic extraction method to extract parasitic elements of modified geometries efficiently, where the incremental extraction is used as a part of the routing optimization process to improve the optimization runtime and increase the optimization accuracy

Field solver technologies for variation-aware interconnect parasitic extraction

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 207-213).Advances in integrated circuit manufacturing technologies have enabled high density onchip integration by constantly scaling down the device and interconnect feature size. As a consequence of the ongoing technology scaling (from 45nm to 32nm, 22nm and beyond), geometrical variabilities induced by the uncertainties in the manufacturing processes are becoming more significant. Indeed, the dimensions and shapes of the manufactured devices and interconnect structures may vary by up to 40% from their design intent. The effect of such variabilities on the electrical characteristics of both devices and interconnects must be accurately evaluated and accounted for during the design phase. In the last few years, there have been several attempts to develop variation-aware extraction algorithms, i.e. algorithms that evaluate the effect of geometrical variabilities on the electrical characteristics of devices and interconnects. However, most algorithms remain computationally very expensive. In this thesis the focus is on variation-aware interconnect parasitic extraction. In the first part of the thesis several discretization-based variation-aware solver techniques are developed. The first technique is a stochastic model reduction algorithm (SMOR) The SMOR guarantees that the statistical moments computed from the reduced model are the same as those of the full model. The SMOR works best for problems in which the desired electrical property is contained in an easily defined subspace.(cont.) The second technique is the combined Neumann Hermite expansion (CNHE). The CNHE combines the advantages of both the standard Neumann expansion and the standard stochastic Galerkin method to produce a very efficient extraction algorithm. The CNHE works best in problems for which the desired electrical property (e.g. impedance) is accurately expanded in terms of a low order multivariate Hermite expansion. The third technique is the stochastic dominant singular vectors method (SDSV). The SDSV uses stochastic optimization in order to sequentially determine an optimal reduced subspace, in which the solution can be accurately represented. The SDSV works best for large dimensional problems, since its complexity is almost independent of the size of the parameter space. In the second part of the thesis, several novel discretization-free variation aware extraction techniques for both resistance and capacitance extraction are developed. First we present a variation-aware floating random walk (FRW) to extract the capacitance/resistance in the presence of non-topological (edge-defined) variations. The complexity of such algorithm is almost independent of the number of varying parameters. Then we introduce the Hierarchical FRW to extract the capacitance/resistance of a very large number of topologically different structures, which are all constructed from the same set of building blocks. The complexity of such algorithm is almost independent of the total number of structures. All the proposed techniques are applied to a variety of examples, showing orders of magnitude reduction in the computational time compared to the standard approaches. In addition, we solve very large dimensional examples that are intractable when using standard approaches.by Tarek Ali El-Moselhy.Ph.D

Numerical Methods for Parasitic Extraction of Advanced Integrated Circuits

FFinFETs, also known as Fin Field Effect Transistors, are a type of non-planar transistors used in the modern integrated circuits. Fast and accurate parasitic capacitance and resistance extraction is crucial in the design and verification of Fin- FET integrated circuits. Though there are wide varieties of techniques available for parasitic extraction, FinFETs still pose tremendous challenges due to the complex geometries and user model of FinFETs. In this thesis, we propose three practical techniques for parasitic extraction of FinFET integrated circuits. The first technique we propose is to solve the dilemma that foundries and IP vendors face to protect the sensitive information which is prerequisite for accurate parasitic extraction. We propose an innovative solution to the challenge, by building a macro model around any region in 2D/3D on a circuit where foundries or IP vendors wish to hide information, yet the macro model allows accurate capacitance extraction inside and outside of the region. The second technique we present is to reduce the truncation error introduced by the traditional Neumann boundary condition. We make a fundamental contribution to the theory of field solvers by proposing a class of absorbing boundary conditions, which when placed on the boundary of the numerical region, will act as if the region extends to infinity. As a result, we can significantly reduce the size of the numerical region, which in turn reduces the run time without sacrificing accuracy. Finally, we improve the accuracy and efficiency of resistance extraction for Fin-FET with non-orthogonal resistivity interface through FVM and IFEM. The performance of FVM is comparable to FEM but with better stability since the conservation law is guaranteed. The IFEM is even better in both efficiency and mesh generation cost than other methods, including FDM, FEM and FVM. The proposed methods are based on rigorous mathematical derivations and verified through experimental results on practical example

Numerical Methods for Parasitic Extraction of Advanced Integrated Circuits

FFinFETs, also known as Fin Field Effect Transistors, are a type of non-planar transistors used in the modern integrated circuits. Fast and accurate parasitic capacitance and resistance extraction is crucial in the design and verification of Fin- FET integrated circuits. Though there are wide varieties of techniques available for parasitic extraction, FinFETs still pose tremendous challenges due to the complex geometries and user model of FinFETs. In this thesis, we propose three practical techniques for parasitic extraction of FinFET integrated circuits. The first technique we propose is to solve the dilemma that foundries and IP vendors face to protect the sensitive information which is prerequisite for accurate parasitic extraction. We propose an innovative solution to the challenge, by building a macro model around any region in 2D/3D on a circuit where foundries or IP vendors wish to hide information, yet the macro model allows accurate capacitance extraction inside and outside of the region. The second technique we present is to reduce the truncation error introduced by the traditional Neumann boundary condition. We make a fundamental contribution to the theory of field solvers by proposing a class of absorbing boundary conditions, which when placed on the boundary of the numerical region, will act as if the region extends to infinity. As a result, we can significantly reduce the size of the numerical region, which in turn reduces the run time without sacrificing accuracy. Finally, we improve the accuracy and efficiency of resistance extraction for Fin-FET with non-orthogonal resistivity interface through FVM and IFEM. The performance of FVM is comparable to FEM but with better stability since the conservation law is guaranteed. The IFEM is even better in both efficiency and mesh generation cost than other methods, including FDM, FEM and FVM. The proposed methods are based on rigorous mathematical derivations and verified through experimental results on practical example

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Advanced analog layout design automation in compliance with density uniformity

To fabricate a reliable integrated circuit chip, foundries follow specific design rules and layout processing techniques. One of the parameters, which affect circuit performance and final electronic product quality, is the variation of thickness for each semiconductor layer within the fabricated chips. The thickness is closely dependent on the density of geometric features on that layer. Therefore, to ensure consistent thickness, foundries normally have to seriously control distribution of the feature density on each layer by using post-processing operations. In this research, the methods of controlling feature density distribution on different layers of an analog layout during the process of layout migration from an old technology to a new one or updated design specifications in the same technology have been investigated. We aim to achieve density-uniformity-aware layout retargeting for facilitating manufacturing process in the advanced technologies. This can offer an advantage right to the design stage for the designers to evaluate the effects of applying density uniformity to their drafted layouts, which are otherwise usually done by the foundries at the final manufacturing stage without considering circuit performance. Layout modification for density uniformity includes component position change and size modification, which may induce crosstalk noise caused by extra parasitic capacitance. To effectively control this effect, we have also investigated and proposed a simple yet accurate analytic method to model the parasitic capacitance on multi-layer VLSI chips. Supported by this capacitance modeling research, a unique methodology to deal with density-uniformity-aware analog layout retargeting with the capability of parasitic capacitance control has been presented. The proposed operations include layout geometry position rearrangement, interconnect size modification, and extra dummy fill insertion for enhancing layout density uniformity. All of these operations are holistically coordinated by a linear programming optimization scheme. The experimental results demonstrate the efficacy of the proposed methodology compared to the popular digital solutions in terms of minimum density variation and acute parasitic capacitance control

Rapid solution of potential integral equations in complicated 3-dimensional geometries

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (p. 133-137).by Joel Reuben Phillips.Ph.D

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc