Application of Expectation-Maximization Algorithm to the Detection of a Direct-Sequence Signal in Pulsed Noise Jamming

We consider the detection of a direct-sequence spread-spectrum signal received in a pulsed noise jamming environment. The expectation-maximization algorithm is used to estimate the unknown jammer parameters and hence obtain a decision on the binary signal based on the estimated likelihood functions. The probability of error performance of the algorithm is simulated for a repeat code and a (7,4) block code. Simulation results show that at low signal-to-thermal noise ratio and high jammer power, the EM detector performs significantly better than the hard limiter and somewhat better than the soft limiter. Also, at low SNR, there is little degradation as compared to the maximum-likelihood detector with true jammer parameters. At high SNR, the soft limiter outperforms the EM detector

Bayesian Estimation of a Gaussian source in Middleton's Class-A Impulsive Noise

The paper focuses on minimum mean square error (MMSE) Bayesian estimation for a Gaussian source impaired by additive Middleton's Class-A impulsive noise. In addition to the optimal Bayesian estimator, the paper considers also the soft-limiter and the blanker, which are two popular suboptimal estimators characterized by very low complexity. The MMSE-optimum thresholds for such suboptimal estimators are obtained by practical iterative algorithms with fast convergence. The paper derives also the optimal thresholds according to a maximum-SNR (MSNR) criterion, and establishes connections with the MMSE criterion. Furthermore, closed form analytic expressions are derived for the MSE and the SNR of all the suboptimal estimators, which perfectly match simulation results. Noteworthy, these results can be applied to characterize the receiving performance of any multicarrier system impaired by a Gaussian-mixture noise, such as asymmetric digital subscriber lines (ADSL) and power-line communications (PLC).Comment: 30 pages, 13 figures, part of this work has been submitted to IEEE Signal Processing Letter

Performance analysis of SWIPT relaying systems in the presence of impulsive noise

We develop an analytical framework to characterize the effect of impulsive noise on the performance of relay-assisted simultaneous wireless information and power transfer (SWIPT) systems. We derive novel closed-form expressions for the pairwise error probability (PEP) considering two variants based on the availability of channel state information (CSI), namely, blind re-laying and CSI-assisted relaying. We further consider two energy harvesting (EH) techniques, i.e., instantaneous EH (IEH) and average EH (AEH). Capitalizing on the derived analytical results, we present a detailed numerical investigation of the diversity order for the underlying scenarios under the impulsive noise assumption. For the case when two relays and the availability of a direct link, it is demonstrated that the considered SWIPT system with blind AEH-relaying is able to achieve an asymptotic diversity order of less than 3, which is equal to the diversity order achieved by CSI-assisted IEH-relaying. This result suggests that, by employing the blind AEH relaying, the power consumption of the network can be reduced, due to eliminating the need of CSI estimation. This can be achieved without any performance loss. Our results further show that placing the relays close to the source can significantly mitigate the detrimental effects of impulsive noise. Extensive Monte Carlo simulation results are presented to validate the accuracy of the proposed analytical framework

IEEE TRANSACTIONS ON COMMUNICATIONS, ACCEPTED FOR PUBLICATION 1 Decision Boundary Evaluation of Optimum and Suboptimum Detectors in Class-A Interference

Abstract-The Middleton Class-A (MCA) model is one of the most accepted models for narrow-band impulsive interference superimposed to additive white Gaussian noise (AWGN). The MCA density consists of a weighted linear combination of infinite Gaussian densities, which leads to a non-tractable form of the optimum detector. To reduce the receiver complexity, one can start with a two-term approximation of the MCA model, which has only two noise states (Gaussian and impulsive state). Our objective is to introduce a simple method to estimate the noise state at the receiver and accordingly, reduce the complexity of the optimum detector. Furthermore, we show for the first time how the decision boundaries of binary signals in MCA noise should look like. In this context, we provide a new analysis of the behavior of many suboptimum detectors such as a linear detector, a locally optimum detector (LOD), and a clipping detector. Based on this analysis, we insert a new clipping threshold for the clipping detector, which significantly improves the bit-error rate performance

BER Performance Improvement in UWA Communication via Spatial Diversity

In present era while wireless communication has become an integral part of our life, the advancements in underwater communications (UWA) is still seem farfetched. Underwater communication is typically essential because of its ability to collect information from remote undersea locations. It don’t use radio signals for signal transmission as they can propagate over extremely short distance because of degradation in signal strength due to salinity of water, rather it uses acoustic waves. The underwater acoustic channel has many characteristics which makes receivers very difficult to be realized. Some of the characteristics are frequency dependent propagation loss, severe Doppler spread multipath, low speed of sound. Due to motion of transmitter and receiver the time variability and multipath makes underwater channel very difficult to be estimated. There are various channel estimation techniques to find out channel impulse response but in this thesis we have considered a flat slow fading channel modeled by Nakagami-m distribution. Noise in underwater communication channel is frequency dependent in nature as for a particular range of frequency of operation one among the various noise sources will be dominant. Here they don’t necessarily follow Gaussian statistics rather follows Generalized Gaussian statistics with decaying power spectral density. The flexible parametric form of this statistics makes it useful to fit any source of underwater noise source. In this thesis we have gone through two step approach. In the first step, we have considered transmission of information in presence of noise only and designed a suboptimal maximum likelihood detector. We have compared the performance of this proposed detector with the conventional Gaussian detector where decision is taken based on a single threshold value and the threshold value is calculated by using various techniques. Here it is being observed that the ML detector outperforms the Gaussian detectors and the performance can be improved further by exploiting the multipath components. In the second step we have considered channel along with noise and have designed a ML detector where we have considered the receiver is supplied with two copies of the same transmitted signal and have gone through a two-dimensional analysis. Again we compared the performance with conventional maximal ratio combiner where we can observe the ML detector performance is better. Further we have incorporated selection combining along with these detectors and compared the performance. Simulation results shows that the proposed detector always outperforms the existing detectors in terms of error performance

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process