1,453 research outputs found
Hardware acceleration architectures for MPEG-Based mobile video platforms: a brief overview
This paper presents a brief overview of past and current hardware acceleration (HwA) approaches that have been proposed for the most computationally intensive compression tools of the MPEG-4 standard. These approaches are classified based on their historical evolution and architectural approach. An analysis of both evolutionary and functional classifications is carried out in order to speculate on the possible trends of the HwA architectures to be employed in mobile video platforms
Efficient hardware architectures for MPEG-4 core profile
Efficient hardware acceleration architectures are proposed for the most demandingMPEG-4 core profile algorithms, namely; texture motion estimation (TME), binary motion estimation (BME)and the shape adaptive discrete cosine transform (SA-DCT). The proposed ME designs may also be used for H.264, since both architectures can handle variable block sizes. Both ME architectures employ early termination techniques that reduce latency and save needless memory accesses and power consumption. They also use a pixel subsampling technique to facilitate parallelism,
while balancing the computational load. The BME datapath also saves operations by using Run Length Coded (RLC) pixel addressing. The SA-DCT module has a re-configuring multiplier-less serial datapath using adders and multiplexers only to improve area and power. The SA-DCT packing steps are done using a minimal switching addressing scheme with guarded evaluation. All three modules have been synthesised targeting the WildCard-II FPGA benchmarking platform adopted by the MPEG-4 Part9 reference hardware group
Low power techniques for video compression
This paper gives an overview of low-power techniques proposed in the literature for mobile multimedia and Internet applications. Exploitable aspects are discussed in the behavior of different video compression tools. These power-efficient solutions are then classified by synthesis domain and level of abstraction. As this paper is meant to be a starting point for further research in the area, a lowpower hardware & software co-design methodology is outlined in the end as a possible scenario for video-codec-on-a-chip implementations on future mobile multimedia platforms
Energy-efficient acceleration of MPEG-4 compression tools
We propose novel hardware accelerator architectures for the most computationally demanding algorithms of the MPEG-4 video compression standard-motion estimation, binary motion estimation (for shape coding), and the forward/inverse discrete cosine transforms (incorporating shape adaptive modes). These accelerators have been designed using general low-energy design philosophies at the algorithmic/architectural abstraction levels. The themes of these philosophies are avoiding waste and trading area/performance for power and energy gains. Each core has been synthesised targeting TSMC 0.09
μm TCBN90LP technology, and the experimental results presented in this paper show that the proposed cores improve upon the prior art
A low complexity hardware architecture for motion estimation
This paper tackles the problem of accelerating motion estimation for video processing. A novel architecture using binary data is proposed, which attempts to reduce power consumption. The solution exploits redundant operations in the sum of absolute differences (SAD) calculation, by a mechanism known as early termination. Further data redundancies are exploited by using a run length coding addressing scheme, where access to pixels which do not contribute to the final SAD value is minimised. By using these two techniques operations and memory accesses are reduced by 93.29% and 69.17% respectively relative to a systolic array implementation
Energy efficient enabling technologies for semantic video processing on mobile devices
Semantic object-based processing will play an increasingly important role in future multimedia systems due to the ubiquity of digital multimedia capture/playback technologies and increasing storage capacity. Although the object based paradigm has many undeniable benefits, numerous technical challenges remain before the applications becomes pervasive, particularly on computational constrained mobile devices. A fundamental issue is the ill-posed problem of semantic object segmentation. Furthermore, on battery powered mobile computing devices, the additional algorithmic complexity of semantic object based processing compared to conventional video processing is highly undesirable both from a real-time operation and battery life perspective. This
thesis attempts to tackle these issues by firstly constraining the solution space and focusing on the
human face as a primary semantic concept of use to users of mobile devices. A novel face detection algorithm is proposed, which from the outset was designed to be amenable to be offloaded from the host microprocessor to dedicated hardware, thereby providing real-time performance and
reducing power consumption. The algorithm uses an Artificial Neural Network (ANN), whose topology and weights are evolved via a genetic algorithm (GA). The computational burden of the ANN evaluation is offloaded to a dedicated hardware accelerator, which is capable of processing
any evolved network topology. Efficient arithmetic circuitry, which leverages modified Booth recoding, column compressors and carry save adders, is adopted throughout the design. To tackle the increased computational costs associated with object tracking or object based shape encoding, a novel energy efficient binary motion estimation architecture is proposed. Energy is reduced in the proposed motion estimation architecture by minimising the redundant operations inherent in the binary data. Both architectures are shown to compare favourable with the relevant prior art
MPEG-4 Software Video Encoding
A Thesis submitted in fulfillment of the requirements of the degree of doctor of Philosophy in the University of LondonThis thesis presents a software model that allows a parallel decomposition of the
MPEG-4 video encoder onto shared memory architectures, in order to reduce its
total video encoding time.
Since a video sequence consists of video objects each of which is likely to have
different encoding requirements, the model incorporates a scheduler which
(a) always selects the most appropriate video object for encoding and,
(b) employs a mechanism for dynamically allocating video objects allocation onto
the system processors, based on video object size information.
Further spatial video object parallelism is exploited by applying the single program
multiple data (SPMD) paradigm within the different modules of the MPEG-4
video encoder. Due to the fact that not all macroblocks have the same processing
requirements, the model also introduces a data partition scheme that generates tiles
with identical processing requirements. Since, macroblock data dependencies
preclude data parallelism at the shape encoder the model also introduces a new
mechanism that allows parallelism using a circular pipeline macroblock technique
The encoding time depends partly on an encoder’s computational complexity. This
thesis also addresses the problem of the motion estimation, as its complexity has a
significant impact on the encoder’s complexity. In particular, two fast motion
estimation algorithms have been developed for the model which reduce the
computational complexity significantly. The thesis includes experimental results on a four processor shared memory
platform, Origin200
Surveillance centric coding
PhDThe research work presented in this thesis focuses on the development of techniques
specific to surveillance videos for efficient video compression with higher processing
speed. The Scalable Video Coding (SVC) techniques are explored to achieve higher
compression efficiency. The framework of SVC is modified to support Surveillance
Centric Coding (SCC). Motion estimation techniques specific to surveillance videos
are proposed in order to speed up the compression process of the SCC.
The main contributions of the research work presented in this thesis are divided into
two groups (i) Efficient Compression and (ii) Efficient Motion Estimation. The
paradigm of Surveillance Centric Coding (SCC) is introduced, in which coding aims
to achieve bit-rate optimisation and adaptation of surveillance videos for storing and
transmission purposes. In the proposed approach the SCC encoder communicates
with the Video Content Analysis (VCA) module that detects events of interest in
video captured by the CCTV. Bit-rate optimisation and adaptation are achieved by
exploiting the scalability properties of the employed codec. Time segments
containing events relevant to surveillance application are encoded using high spatiotemporal
resolution and quality while the irrelevant portions from the surveillance
standpoint are encoded at low spatio-temporal resolution and / or quality. Thanks to
the scalability of the resulting compressed bit-stream, additional bit-rate adaptation is
possible; for instance for the transmission purposes. Experimental evaluation showed
that significant reduction in bit-rate can be achieved by the proposed approach
without loss of information relevant to surveillance applications.
In addition to more optimal compression strategy, novel approaches to performing
efficient motion estimation specific to surveillance videos are proposed and
implemented with experimental results. A real-time background subtractor is used to
detect the presence of any motion activity in the sequence. Different approaches for
selective motion estimation, GOP based, Frame based and Block based, are
implemented. In the former, motion estimation is performed for the whole group of
pictures (GOP) only when a moving object is detected for any frame of the GOP.
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While for the Frame based approach; each frame is tested for the motion activity and
consequently for selective motion estimation. The selective motion estimation
approach is further explored at a lower level as Block based selective motion
estimation. Experimental evaluation showed that significant reduction in
computational complexity can be achieved by applying the proposed strategy. In
addition to selective motion estimation, a tracker based motion estimation and fast
full search using multiple reference frames has been proposed for the surveillance
videos.
Extensive testing on different surveillance videos shows benefits of
application of proposed approaches to achieve the goals of the SCC
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