Partial element equivalent circuit models in the solution of the electric field integral equation

3-D electromagnetic methods are fundamental design tools for complex high-speed systems. Among the integral equation-based techniques, the Partial Element Equivalent Circuit (PEEC) method has received a special attention in interconnect modeling, where mixed electromagnetic/circuit problems need to be solved. Retardation effects and the resulting delays must be taken into account and included in the modeling, when signal waveform rise times decrease and the corresponding frequency content increases or the geometric dimensions become electrically long. In this case, the enforcement of the Kirchhoff laws to PEEC delayed models leads to a set of delayed differential equations in a neutral form. The aim of this contribution is to present an overview of the PEEC method with special focus on the analysis of electrically long structures that require taking delays into account

Analytic Delay Model of RLC Interconnects using Numerical Inversion of the Laplace Transform

Signal integrity analysis for on-chip interconnect becomes increasingly important in high-speed designs. SPICE, a conventional circuit simulator, can provide accurate prediction for interconnects, however, using SPICE is extremely computationally expensive. On the other hand, explicit moment matching technique can produce unstable poles for highly accurate approximations and implicit moment matching technique can obtain more accurate approximations at the expense of computational complexity. This thesis presents an analytic model to efficiently estimate the signal delays of RLC on-chip interconnects. It uses the numerical inversion of Laplace transform (NILT) to obtain time function, suitable for transient analysis. Since the integration formula of the NILT is numerically stable for higher order approximations, the developed algorithm provides a mechanism to increase the accuracy for delay estimation. Numerical examples are implemented and compared with HSPICE, two-pole model and Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) to illustrate the efficiency and validity of the proposed work

How affine arithmetic helps beat uncertainties in electrical systems

The ever-increasing impact of uncertainties in electronic circuits and systems is requiring the development of robust design tools capable of taking this inherent variability into account. Due to the computational inefficiency of repeated design trials, there has been a growing demand for smart simulation tools that can inherently and effectively capture the results of parameter variations on the system responses. To improve product performance, improve yield and reduce design cost, it is particularly relevant for the designer to be able to estimate worst-case responses. Within this framework, the article addresses the worst-case simulation of lumped and distributed electrical circuits. The application of interval-based methods, like interval analysis, Taylor models and affine arithmetic, is discussed and compared. The article reviews in particular the application of the affine arithmetic to complex algebra and fundamental matrix operations for the numerical frequency-domain simulation. A comprehensive and unambiguous discussion appears in fact to be missing in the available literature. The affine arithmetic turns out to be accurate and more efficient than traditional solutions based on Monte Carlo analysis. A selection of relevant examples, ranging from linear lumped circuits to distributed transmission-line structures, is used to illustrate this technique

Addressing Computational Complexity of High Speed Distributed Circuits Using Model Order Reduction

Advanced in the fabrication technology of integrated circuits (ICs) over the last couple of years has resulted in an unparalleled expansion of the functionality of microelectronic systems. Today’s ICs feature complex deep-submicron mixed-signal designs and have found numerous applications in industry due to their lower manufacturing costs and higher performance levels. The tendency towards smaller feature sizes and increasing clock rates is placing higher demands on signal integrity design by highlighting previously negligible interconnect effects such as distortion, reflection, ringing, delay, and crosstalk. These effects if not predicted in the early stages of the design cycle can severely degrade circuit performance and reliability. The objective of this thesis is to develop new model order reduction (MOR) techniques to minimize the computational complexity of non-linear circuits and electronic systems that have delay elements. MOR techniques provide a mechanism to generate reduced order models from the detailed description of the original modified nodal analysis (MNA) formulation. The following contributions are made in this thesis: 1. The first project presents a methodology for reduction of Partial Element Equivalent Circuit (PEEC) models. PEEC method is widely used in electromagnetic compatibility and signal integrity problems in both the time and frequency domains. The PEEC model with retardation has been applied to 3-D analysis but often result in large and dense matrices, which are computationally expensive to solve. In this thesis, a new moment matching technique based on Multi-order Arnoldi is described to model PEEC networks with retardation. 2. The second project deals with developing an efficient model order reduction algorithm for simulating large interconnect networks with nonlinear elements. The proposed methodology is based on a multidimensional subspace method and uses constraint equations to link the nonlinear elements and biasing sources to the reduced order model. This approach significantly improves the simulation time of distributed nonlinear systems, since additional ports are not required to link the nonlinear elements to the reduced order model, yielding appreciable savings in the size of the reduced order model and computational time. 3. A parameterized reduction technique for nonlinear systems is presented. The proposed method uses multidimensional subspace and variational analysis to capture the variances of design parameters and approximates the weakly nonlinear functions as a Taylor series. An SVD approach is presented to address the efficiency of reduced order model. The proposed methodology significantly improves the simulation time of weakly nonlinear systems since the size of the reduced system is smaller than the original system and a new reduced model is not required each time a design parameter is changed

Delay Extraction based Macromodeling with Parallel Processing for Efficient Simulation of High Speed Distributed Networks

This thesis attempts to address the computational demands of accurate modeling of high speed distributed networks such as interconnect networks and power distribution networks. In order to do so, two different approaches towards modeling of high speed distributed networks are considered. One approach deals with cases where the physical characteristics of the network are not known and the network is characterized by its frequency domain tabulated data. Such examples include long interconnect networks described by their Y parameter data. For this class of problems, a novel delay extraction based IFFT algorithm has been developed for accurate transient response simulation. The other modeling approach is based on a detailed knowledge of the physical and electrical characteristics of the network and assuming a quasi transverse mode of propagation of the electromagnetic wave through the network. Such problems may include two dimensional (2D) and three dimensional (3D) power distribution networks with known geometry and materials. For this class of problem, a delay extraction based macromodeling approaches is proposed which has been found to be able to capture the distributed effects of the network resulting in more compact and accurate simulation compared to the state-of-the-art quasi-static lumped models. Furthermore, waveform relaxation based algorithms for parallel simulations of large interconnect networks and 2D power distribution networks is also presented. A key contribution of this body of work is the identification of naturally parallelizable and convergent iterative techniques that can divide the computational costs of solving such large macromodels over a multi-core hardware

Transient simulation of complex electronic circuits and systems operating at ultra high frequencies

The electronics industry worldwide faces increasingly difficult challenges in a bid to produce ultra-fast, reliable and inexpensive electronic devices. Electronic manufacturers rely on the Electronic Design Automation (EDA) industry to produce consistent Computer A id e d Design (CAD) simulation tools that w ill enable the design of new high-performance integrated circuits (IC), the key component of a modem electronic device. However, the continuing trend towards increasing operational frequencies and shrinking device sizes raises the question of the capability of existing circuit simulators to accurately and efficiently estimate circuit behaviour. The principle objective of this thesis is to advance the state-of-art in the transient simulation of complex electronic circuits and systems operating at ultra high frequencies. Given a set of excitations and initial conditions, the research problem involves the determination of the transient response o f a high-frequency complex electronic system consisting of linear (interconnects) and non-linear (discrete elements) parts with greatly improved efficien cy compared to existing methods and with the potential for very high accuracy in a way that permits an effective trade-off between accuracy and computational complexity. High-frequency interconnect effects are a major cause of the signal degradation encountered b y a signal propagating through linear interconnect networks in the modem IC. Therefore, the development of an interconnect model that can accurately and efficiently take into account frequency-dependent parameters of modem non-uniform interconnect is of paramount importance for state-of-art circuit simulators. Analytical models and models based on a set of tabulated data are investigated in this thesis. Two novel, h igh ly accurate and efficient interconnect simulation techniques are developed. These techniques combine model order reduction methods with either an analytical resonant model or an interconnect model generated from frequency-dependent sparameters derived from measurements or rigorous full-wave simulation. The latter part o f the thesis is concerned with envelope simulation. The complex mixture of profoundly different analog/digital parts in a modern IC gives rise to multitime signals, where a fast changing signal arising from the digital section is modulated by a slower-changing envelope signal related to the analog part. A transient analysis of such a circuit is in general very time-consuming. Therefore, specialised methods that take into account the multi-time nature o f the signal are required. To address this issue, a novel envelope simulation technique is developed. This technique combines a wavelet-based collocation method with a multi-time approach to result in a novel simulation technique that enables the desired trade-off between the required accuracy and computational efficiency in a simple and intuitive way. Furthermore, this new technique has the potential to greatly reduce the overall design cycle

Modeling for the Computer-Aided Design of Long Interconnects

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