2,196 research outputs found
Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies
CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections
Reduction of 1/f Noise in MOSFETS by Switched Bias Techniques
Switched Biasing is presented as a technique for reducing the 1/f noise in MOSFETS. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its 1/f noise!! The history of the discovery of the effect and the main experimental results obtained so far will be reviewed
Integrated chaos generators
This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.ComisiĂłn Interministerial de Ciencia y TecnologĂa 1FD97-1611(TIC)European Commission ESPRIT 3110
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