8 research outputs found

    An Efficient Combined Demosaicing and Zooming Algorithm for Digital Camera

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    An efficient combined demosaicing and zooming algorithm for digital camera

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    2007-2008 > Academic research: refereed > Refereed conference paperVersion of RecordPublishe

    An Adaptive Color Filter Array Interpolation Algorithm for Digital Camera

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    Partition-based Interpolation for Color Filter Array Demosaicking and Super-Resolution Reconstruction

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    A class of partition-based interpolators that addresses a variety of image interpolation applications are proposed. The proposed interpolators first partition an image into a finite set of partitions that capture local image structures. Missing high resolution pixels are then obtained through linear operations on neighboring pixels that exploit the captured image structure. By exploiting the local image structure, the proposed algorithm produces excellent performance on both edge and uniform regions. The presented results demonstrate that partition-based interpolation yields results superior to traditional and advanced algorithms in the applications of color filter array (CFA) demosaicking and super-resolution reconstruction

    High performance image demosaicing hardware designs

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    Most digital cameras capture only one color channel (red, green, or blue) per pixel, because capturing three color channels per pixel would require three image sensors which increases the cost of digital cameras. Therefore, only one image sensor is used, and images pass through a color filter array (CFA) before being captured by the image sensor. Bayer pattern is the most commonly used CFA pattern in digital cameras. Demosaicing is the process of reconstructing the missing color channels of the pixels in the color filtered image using their available neighboring pixels. There are many image demosaicing algorithms with varying reconstructed image quality and computational complexity. In this thesis, high performance hardware architectures are designed for three high quality image demosaicing algorithms, and the proposed hardware architectures are implemented on FPGA. A high performance hardware architecture for Effective Color Interpolation (ECI) demosaicing algorithm is proposed. A modified version of Enhanced ECI demosaicing algorithm and a high performance hardware architecture for this image demosaicing algorithm are proposed. A hybrid ECI and Alternating Projections demosaicing algorithm and a high performance hardware architecture for this image demosaicing algorithm are proposed. The proposed hardware architectures are implemented using Verilog HDL. The Verilog RTL codes are mapped to Xilinx Virtex 6 FPGA. The proposed FPGA implementations are verified with post place & route simulations. They are capable of processing 160, 118, and 119 full HD images per second

    High performance high quality image demosaicing hardware designs

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    Since capturing three color channels (red, green, and blue) per pixel increases the cost of digital cameras, most digital cameras capture only one color channel per pixel using a single image sensor. The images pass through a color filter array before being captured by the image sensor. Demosaicing is the process of reconstructing the missing color channels of the pixels in the color filtered image using their available neighboring pixels. There are many image demosaicing algorithms with varying reconstructed image quality and computational complexity. In this thesis, high performance hardware architectures are designed for two high quality image demosaicing algorithms with high computational complexity. The proposed hardware architectures are implemented on an FPGA. A high performance Alternating Projections (AP) image demosaicing hardware is proposed. This is the first AP image demosaicing hardware in the literature. A high performance Enhanced Effective Color Interpolation (EECI) image demosaicing hardware is proposed. This is the first EECI image demosaicing hardware in the literature. The proposed hardware architectures are implemented using Verilog HDL. The Verilog RTL codes are mapped to a Xilinx Virtex 6 FPGA. The proposed FPGA implementations are verified with post place & route simulations. They can process 31 and 94 full HD (1920x1080) images per second, respectively

    Super resolution and dynamic range enhancement of image sequences

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    Camera producers try to increase the spatial resolution of a camera by reducing size of sites on sensor array. However, shot noise causes the signal to noise ratio drop as sensor sites get smaller. This fact motivates resolution enhancement to be performed through software. Super resolution (SR) image reconstruction aims to combine degraded images of a scene in order to form an image which has higher resolution than all observations. There is a demand for high resolution images in biomedical imaging, surveillance, aerial/satellite imaging and high-definition TV (HDTV) technology. Although extensive research has been conducted in SR, attention has not been given to increase the resolution of images under illumination changes. In this study, a unique framework is proposed to increase the spatial resolution and dynamic range of a video sequence using Bayesian and Projection onto Convex Sets (POCS) methods. Incorporating camera response function estimation into image reconstruction allows dynamic range enhancement along with spatial resolution improvement. Photometrically varying input images complicate process of projecting observations onto common grid by violating brightness constancy. A contrast invariant feature transform is proposed in this thesis to register input images with high illumination variation. Proposed algorithm increases the repeatability rate of detected features among frames of a video. Repeatability rate is increased by computing the autocorrelation matrix using the gradients of contrast stretched input images. Presented contrast invariant feature detection improves repeatability rate of Harris corner detector around %25 on average. Joint multi-frame demosaicking and resolution enhancement is also investigated in this thesis. Color constancy constraint set is devised and incorporated into POCS framework for increasing resolution of color-filter array sampled images. Proposed method provides fewer demosaicking artifacts compared to existing POCS method and a higher visual quality in final image
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