Copper Metal for Semiconductor Interconnects

Resistance-capacitance (RC) delay produced by the interconnects limits the speed of the integrated circuits from 0.25 mm technology node. Copper (Cu) had been used to replace aluminum (Al) as an interconnecting conductor in order to reduce the resistance. In this chapter, the deposition method of Cu films and the interconnect fabrication with Cu metallization are introduced. The resulting integration and reliability challenges are addressed as well

Study of Tantalum nitride diffusion barrier films for coppper interconnect technology

As technology progressed to ultra - large scale integration leading to smaller and smaller devices, there are continuous challenges in the fields of materials, processes and circuit designs. Copper is the interconnect material of choice because of its low electrical resistivity and high electromigration resistance. However, copper is quite mobile in silicon at elevated temperatures. Therefore, to prevent the diffusion of copper into silicon, a diffusion barrier layer that has fewer grain boundaries, good adhesion to Si and Si02, high thermal and electrical stability with respect to Cu is necessary. Tantalum nitride compounds have been investigated as potential barrier materials. TaN has a very high melting point of 2950C. It is thermodynamically stable with respect to Cu and has good adhesion to the substrate. It has a dense microstructure and shows good resistance to heavy mobility of Cu in Si and has electrical stability at temperatures upto 750 C. The diffusion barrier properties of Ta and its nitrides for copper metallization at RIT have been investigated. The TaNx films were reactively sputter deposited on Si02 substrates at various N2/AJ- ratios. The influence of nitrogen partial pressure on the electrical and structural properties of the films is studied. It has been observed that as deposited pure Ta is tetragonal, which becomes bcc-Ta with small increase in N2 flow to 5% of the sputtering gas mixture. When the nitrogen flow is increased from 12 up to 20%, amorphous and a mixture of amorphous and crystalline Ta2N phase is formed. The amorphous phase crystallizes when annealed to higher temperatures. An fee- TaN phase is formed at N2 flow of 30%. At higher concentrations of N2; nitrogen rich compounds like Ta5N6, Ta3N5 are formed. During backend semiconductor processing, both Cu and TaN films are subjected to various annealing treatments in N2, 02, and Ar at relatively high temperatures. Since these treatments influence the stability of the metallization it was important to establish the effect of the ambients on the integrity of the copper interconnect. The Cu/TaN/Si02 films were annealed to various temperatures up to 600 C in N2, Ar ambients for 20 min and the thermal stability and barrier effectiveness of the films was studied. Annealing the films to temperatures above 500 C cause de-lamination of films at the Cu/TaN interface, which is attributed to the formation of copper oxides with a high density of voids. This was observed by XRD analyis and SEM. RBS spectra showed diffusion of tantalum into the surface of copper at temperatures ~ 500 to 600 C. Therefore we can conclude that cubic TaN films act as stable barrier films up to 500 C in an inert ambient

Chemical Vapor Deposition of Thin Film Materials for Copper Interconnects in Microelectronics

The packing density of microelectronic devices has increased exponentially over the past four decades. Continuous enhancements in device performance and functionality have been achieved by the introduction of new materials and fabrication techniques. This thesis summarizes the thin film materials and metallization processes by chemical vapor deposition (CVD) developed during my graduate study with Professor Gordon at Harvard University. These materials and processes have the potential to build future generations of microelectronic devices with higher speeds and longer lifetimes. Manganese Silicate Diffusion Barrier: Highly conformal, amorphous and insulating manganese silicate $(MnSi_xO_y)$ layers are formed along the walls of trenches in interconnects by CVD using a manganese amidinate precursor vapor that reacts with the surfaces of the insulators. These $(MnSi_xO_y)$ layers are excellent barriers to diffusion of copper, oxygen and water. Manganese Capping Layer: A selective CVD manganese capping process strengthens the interface between copper and dielectric insulators to improve the electromigration reliability of the interconnects. High selectivity is achieved by deactivating the insulator surfaces using vapors containing reactive methylsilyl groups. Manganese at the Cu/insulator interface greatly increases the strength of adhesion between the copper and the insulator. Bottom-up Filling of Copper and Alloy in Narrow Features: Narrow trenches, with widths narrow than 30 nm and aspect ratios up to 9:1, can be filled with copper or copper-manganese alloy in a bottom-up fashion using a surfactant-catalyzed CVD process. A conformal manganese nitride $(Mn_4N)$ layer serves as a diffusion barrier and adhesion layer. Iodine atoms chemisorb on the $Mn_4N$ layer and are then released to act as a catalytic surfactant on the surface of the growing copper layer to achieve void-free, bottom-up filling. Upon post-annealing, manganese in the alloy diffuses out from the copper and forms a self-aligned barrier in the surface of the insulator. Conformal Seed Layers for Plating Through-Silicon Vias: Through-silicon vias (TSV) will speed up interconnections between chips. Conformal, smooth and continuous seed layers in TSV holes with aspect ratios greater than 25:1 can be prepared using vapor deposition techniques. $Mn_4N$ is deposited conformally on the silica surface by CVD to provide strong adhesion at Cu/insulator interface. Conformal copper or Cu-Mn alloy seed layers are then deposited by an iodine-catalyzed direct-liquid-injection (DLI) CVD process.Chemistry and Chemical Biolog

Adhesion in a Copper-Ruthenium Multilayer Nano-scale Structure and the Use of a Miedema Plot to Select a Diffusion Barrier Metal for Copper Metallization

abstract: Miedema's plot is used to select the Cu/metal barrier for Cu metallization.The Cu/metal barrier system selected should have positive heat of formation (Hf) so that there is no intermixing between the two layers. In this case, Ru is chosen as a potential candidate, and then the barrier properties of sputtered Cu/Ru thin films on thermally grown SiO2 substrates are investigated by Rutherford backscattering spectrometry (RBS), X-ray diffractometry (XRD), and electrical resistivity measurement. The Cu/Ru/SiO2 samples are analyzed prior to and after vacuum annealing at various temperatures of 400, 500, and 600 oC and at different interval of times of 0.5, 1 and 2 hrs for each temperature. Backscattering analysis indicate that both the copper and ruthenium thin films are thermally stable at high temperature of 600 oC, without any interdiffusion and chemical reaction between Cu and Ru thin films. No new phase formation is observed in any of the Cu/Ru/SiO2 samples. The XRD data indicate no new phase formation in any of the annealed Cu/Ru/SiO2 samples and confirmed excellent thermal stability of Cu on Ru layer. The electrical resistivity measurement indicated that the electrical resistivity value of the copper thin films annealed at 400, 500, and 600 oC is essentially constant and the copper films are thermally stable on Ru, no reaction occurs between copper films and Ru the layer. Cu/Ru/SiO2 multilayered thin film samples have been shown to possess good mechanical strength and adhesion between the Cu and Ru layers compared to the Cu/SiO2 thin film samples. The strength evaluation is carried out under static loading conditions such as nanoindentation testing. In this study, evaluation and comparison is donebased on the dynamic deformation behavior of Cu/Ru/SiO2 and Cu/SiO2 samples under scratch loading condition as a measure of tribological properties. Finally, the deformation behavior under static and dynamic loading conditions is understood using the scanning electron microscope (SEM) and the focused ionbeam imaging microscope (FIB) for topographical and cross-sectional imaging respectively.Dissertation/ThesisM.S. Materials Science and Engineering 201

Piin läpivientien luotettavuus ja elinikä termisessä rasituksessa

Through-silicon via (TSV) is one of the key technologies for three-dimensional (3D) integrated circuits (ICs). TSVs enable vertical electrical connections between components which greatly reduces interconnection lengths. Regardless of all the promise the technique has shown, there are still major obstacles surrounding reliability and the cost of fabrication of the TSV structure. The first part of the thesis is a literature survey that focuses on different failure mechanisms of TSVs. In addition, different fabrication and design choices of TSVs are presented with the focus being on their effect on reliability. The experimental part of the thesis presents reliability and lifetime assessment of tapered partially copper-filled blind TSVs under thermal cycling. The reliability test was carried out with nine samples. Six of them had 420 vias and three of them had 1400 vias in a daisy chain structure. Finite element method (FEM) was used to predict the critical failure locations of the TSV structure. Lifetime was predicted by Weibull analysis. The cross-sections of the test samples were prepared by molding, mechanical grinding and polishing and analyzed by scanning electron microscope (SEM). Electrical measurements showed almost constant resistance increase in the samples before failures were noticed. The first failed sample was noticed after 200 cycles and the last at 4000 cycles. Lifetime of TSVs under thermal cycling was proven to be acceptable with used failure criterion. According to Weibull analysis, about 10 % of the samples with 420 vias will break after 1000 cycles. Sample preparation for imaging was deemed sufficient although the grinding caused artifacts. The simulation results were compared with SEM micrographs. The images showed that the failures were located at the maximum stress areas, identified with FEM simulations, at the bottom of the via. From the SEM images, it was deduced that the defects initiated from the fabrication process and propagated due to maximum localized stress.Piin läpivienti -rakenteet ovat keskeisessä osassa kolmiulotteisten integroitujen piirien kehityksessä. Piin läpiviennit mahdollistavat komponenttien vertikaalin yhdistämisen toisiinsa, mikä lyhentää huomattavasti niiden välistä etäisyyttä. Kaikista hyvistä puolista huolimatta tekniikalla on vielä haasteita edessään. Niistä suurimmat liittyvät rakenteen luotettavuuteen ja valmistuskustannuksiin. Diplomityön kirjallisessa osuudessa keskitytään piin läpivientien erilaisiin vauriomekanismeihin. Sen lisäksi tutkitaan valmistus- ja suunnitteluratkaisujen vaikutusta läpivientien luotettavuuteen. Kokeellisen osan tarkoituksena on osittain kuparitäytettyjen kaventuvien piin läpivientien luotettavuuden ja eliniän määrittäminen termisessä syklaustestissä. Luotettavuustestaus suoritettiin yhdeksällä näytteellä, joista kuudessa oli 420 läpivientiä ja kolmessa 1400 läpivientiä ketjurakenteessa. Elementtimallintamisen avulla määritettiin kriittiset vauriokohdat läpivientirakenteessa ja elinikä määritettiin Weibull-analyysillä. Näytteiden poikkileikkauksien valmistamiseen käytettiin muovaamista, mekaanista hiomista ja kiillotusta ja analysointi suoritettiin pyyhkäisyelektronimikroskoopilla. Näytteiden resistanssi nousi tasaisesti ennen rikkoutumisten havaitsemista. Ensimmäinen rikkoutuminen huomattiin 200 syklin jälkeen ja viimeinen 4000 syklin kohdalla. Näytteiden luotettavuus osoittautui hyväksi käytetyillä kriteereillä. Weibull-analyysin mukaan 10 % 420 läpiviennin näytteistä rikkoutuu 1000 syklin jälkeen. Karkea arvio voidaan tehdä, että satunnainen läpivienti rikkoutuu 0,024 % todennäköisyydellä 1000 syklin jälkeen. Pyyhkäisyelektronimikroskoopin kuvien perusteella havaittiin, että näytteet rikkoutuivat maksimaalisen rasituksen alueella läpivientien alaosassa. Kuvien perusteella päädyttiin johtopäätökseen, että näytteiden rikkoutumisen aiheuttivat virheet, jotka ovat peräisin valmistusprosessista ja jotka etenivät rakenteessa termisen rasituksen vaikutuksesta

Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect

This work studies various emerging reduced dimensional materials for very large-scale integration (VLSI) interconnects. The prime motivation of this work is to find an alternative to the existing Cu-based interconnect for post-CMOS technology nodes with an emphasis on thermal stability. Starting from the material modeling, this work includes material characterization, exploration of electronic properties, vibrational properties and to analyze performance as a VLSI interconnect. Using state of the art density functional theories (DFT) one-dimensional and two-dimensional materials were designed for exploring their electronic structures, transport properties and their circuit behaviors. Primarily carbon nanotube (CNT), graphene and graphene/copper based interconnects were studied in this work. Being reduced dimensional materials the charge carriers in CNT(1-D) and in graphene (2-D) are quantum mechanically confined as a result of this free electron approximation fails to explain their electronic properties. For same reason Drude theory of metals fails to explain electronic transport phenomena. In this work Landauer transport theories using non-equilibrium Green function (NEGF) formalism was used for carrier transport calculation. For phonon transport studies, phenomenological Fourier’s heat diffusion equation was used for longer interconnects. Semi-classical BTE and Landauer transport for phonons were used in cases of ballistic phonon transport regime. After obtaining self-consistent electronic and thermal transport coefficients, an equivalent circuit model is proposed to analyze interconnects’ electrical performances. For material studies, CNTs of different variants were analyzed and compared with existing copper based interconnects and were found to be auspicious contenders with integrational challenges. Although, Cu based interconnect is still outperforming other emerging materials in terms of the energy-delay product (1.72 fJ-ps), considering the electromigration resistance graphene Cu hybrid interconnect proposed in this dissertation performs better. Ten times more electromigration resistance is achievable with the cost of only 30% increase in energy-delay product. This unique property of this proposed interconnect also outperforms other studied alternative materials such as multiwalled CNT, single walled CNT and their bundles

Process Evaluation and Characterization of Tungsten Nitride as a Diffusion Barrier for Copper Interconnect Technology

The integration of copper (Cu) and dielectric materials has been outlined in the International Technology Roadmap for Semiconductors (ITRS) as a critical goal for future microelectronic devices. A necessity toward achieving this goal is the development of diffusion barriers that resolve the Cu and dielectric incompatibility. The focus of this research examines the potential use of tungsten nitride as a diffusion barrier by characterizing the interfacial properties with Cu and evaluating its process capability for industrial use. Tungsten nitride (β-W2N) development has been carried out using a plasma enhanced chemical vapor deposition (PECVD) technique that utilizes tungsten hexafluoride (WF6), nitrogen (N2), hydrogen (H2), and argon (Ar). Two design of experiments (DOE) were performed to optimize the process with respect to film stoichiometry, resistivity and uniformity across a 200 mm diameter Si wafer. Auger depth profiling showed a 2:1 W:N ratio. X-ray diffraction (XRD) showed a broad peak centered on the β-W2N phase. Film resistivity was 270 mohm-cm and film uniformity 44 %. Secondary ion mass spectroscopy (SIMS) measurements showed good barrier performance for W2N between Cu and SiO2 with no intermixing of the Cu and silicon when annealed to 390o C for 3 hours. Cu nucleation behavior and thermal stability on clean and nitrided tungsten foil (WxN = δ-WN and β-W2N phases) have been characterized by Auger electron spectroscopy (AES) and thermal desorption spectroscopy (TDS) under controlled ultra high vacuum (UHV) conditions. At room temperature, the Auger intensity ratio vs. time plots demonstrates layer by layer Cu growth for the clean tungsten (W) surface and three-dimensional nucleation for the nitride overlayer. Auger intensity ratio vs. temperature measurements for the Cu/W system indicates a stable interface up to 1000 K. For the Cu /WxN/W system, initial Cu diffusion into the nitride overlayer is observed at 550 K

PARAMETERS AFFECTING THE RESISTIVITY OF LP-EBID DEPOSITED COPPER NANOWIRES

Electron Beam Induced Deposition (EBID) is a direct write fabrication process with applications in circuit edit and debug, mask repair, and rapid prototyping. However, it suffers from significant drawbacks, most notably low purity. Work over the last several years has demonstrated that deposition from bulk liquid precursors, rather than organometallic gaseous precursors, results in high purity deposits of low resistivity (LPEBID). In this work, it is shown that the deposits resulting from LP-EBID are only highly conductive when deposited at line doses below 25μC/cm. When the dose exceeds this value, the resulting structure is highly porous providing a poor conductive pathway. It is also shown that beam current has no significant effect on the resistivity of the deposits. Nanowires with resistivity significantly lower than the previous best result of 67μΩ•cm were achieved, with the lowest resistivity being only 6.6μΩ•cm, only a factor of 4 higher than that bulk copper of 1.7μΩ•cm

All-copper chip-to-substrate interconnects for high performance integrated circuit devices

In this work, all-copper connections between silicon microchips and substrates are developed. The semiconductor industry advances the transistor density on a microchip based on the roadmap set by Moore's Law. Communicating with a microprocessor which has nearly one billion transistors is a daunting challenge. Interconnects from the chip to the system (i.e. memory, graphics, drives, power supply) are rapidly growing in number and becoming a serious concern. Specifically, the solder ball connections that are formed between the chip itself and the package are challenging to make and still have acceptable electrical and mechanical performance. These connections are being required to increase in number, increase in power current density, and increase in off-chip operating frequency. Many of the challenges with using solder connections are limiting these areas. In order to advance beyond the limitations of solder for electrical and mechanical performance, a novel approach to creating all-copper connections from the chip-to-substrate has been developed. The development included characterizing the electroless plating and annealing process used to create the connections, designing these connections to be compatible with the stress requirements for fragile low-k devices, and finally by improving the plating/annealing process to become process time competitive with solder. It was found that using a commercially available electroless copper bath for the plating, followed by annealing at 180 C for 1 hour, the shear strength of the copper-copper bond was approximately 165 MPa. This work resulted in many significant conclusions about the mechanism for bonding in the all-copper process and the significance of materials and geometry on the mechanical design for these connections.Ph.D.Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, Jame