ASDTIC control and standardized interface circuits applied to buck, parallel and buck-boost dc to dc power converters

Versatile standardized pulse modulation nondissipatively regulated control signal processing circuits were applied to three most commonly used dc to dc power converter configurations: (1) the series switching buck-regulator, (2) the pulse modulated parallel inverter, and (3) the buck-boost converter. The unique control concept and the commonality of control functions for all switching regulators have resulted in improved static and dynamic performance and control circuit standardization. New power-circuit technology was also applied to enhance reliability and to achieve optimum weight and efficiency

Modeling and analysis of power processing systems: Feasibility investigation and formulation of a methodology

A review is given of future power processing systems planned for the next 20 years, and the state-of-the-art of power processing design modeling and analysis techniques used to optimize power processing systems. A methodology of modeling and analysis of power processing equipment and systems has been formulated to fulfill future tradeoff studies and optimization requirements. Computer techniques were applied to simulate power processor performance and to optimize the design of power processing equipment. A program plan to systematically develop and apply the tools for power processing systems modeling and analysis is presented so that meaningful results can be obtained each year to aid the power processing system engineer and power processing equipment circuit designers in their conceptual and detail design and analysis tasks

Switching Flow-Graph nonlinear modeling technique

A unified graphical modeling technique, “Switching Flow-Graph” is developed to study the nonlinear dynamic behavior of pulse-width-modulated (PWM) switching converters. Switching converters are variable structure systems with linear subsystems. Each subsystem can be represented by a flow-graph. The Switching Flow-Graph is obtained by combining the flowgraphs of the subsystems through the use of switching branches. The Switching Flow-Graph model is easy to derive, and it provides a visual representation of a switching converter system. Experiments demonstrate that the Switching Flow-Graph model has very good accuracy

Maximum power point tracking converter based on the open-circuit voltage method for thermoelectric generators

Thermoelectric generators (TEGs) convert heat energy into electricity in a quantity dependant on the temperature difference across them and the electrical load applied. It is critical to track the optimum electrical operating point through the use of power electronic converters controlled by a Maximum Power Point Tracking (MPPT) algorithm. The MPPT method based on the opencircuit voltage is arguably the most suitable for the linear electrical characteristic of TEGs. This paper presents an innovative way to perform the open-circuit voltage measure during the pseudo-normal operation of the interfacing power electronic converter. The proposed MPPT technique is supported by theoretical analysis and used to control a synchronous buck-boost converter. The prototype MPPT converter is controlled by an inexpensive microcontroller, and a lead-acid battery is used to accumulate the harvested energy. Experimental results using commercial TEG devices prove that the converter accurately tracks the maximum power point during thermal transients. Precise measurements in steady state show that the converter finds the maximum power point with a tracking efficiency of 99.85%

FPGA Design Techniques for Stable Cryogenic Operation

In this paper we show how a deep-submicron FPGA can be modified to operate at extremely low temperatures through modifications in the supporting hardware and in the firmware programming it. Though FPGAs are not designed to operate at a few Kelvin, it is possible to do so on virtue of the extremely high doping levels found in deep-submicron CMOS technology nodes. First, any PCB component, that does not conform with this requirement, is removed. Both the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad-hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA chip. The FPGA is powered with a supply at several meters distance, causing significant IR drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.Comment: The following article has been submitted to Review of Scientific Instruments. If it is published, it will be available on http://rsi.aip.or

Modeling and Analysis of Power Processing Systems (MAPPS). Volume 1: Technical report

Computer aided design and analysis techniques were applied to power processing equipment. Topics covered include: (1) discrete time domain analysis of switching regulators for performance analysis; (2) design optimization of power converters using augmented Lagrangian penalty function technique; (3) investigation of current-injected multiloop controlled switching regulators; and (4) application of optimization for Navy VSTOL energy power system. The generation of the mathematical models and the development and application of computer aided design techniques to solve the different mathematical models are discussed. Recommendations are made for future work that would enhance the application of the computer aided design techniques for power processing systems

v1 concept: designing a voltage mode control as current mode with near time-optimal response for Buck-type converters

This article introduces the v1 concept, that explains how by only measuring the output voltage, designers have information about almost every signal of the power stage. Following the v1 concept, it is explained how to design a traditional type-III voltage mode control to behave like a current mode control with near time-optimal response under load transients. The work is validated in simulations and experimentally on a 300kHz Buck converter

Dual-frequency single-inductor multiple-output (DF-SIMO) power converter topology for SoC applications

Modern mixed-signal SoCs integrate a large number of sub-systems in a single nanometer CMOS chip. Each sub-system typically requires its own independent and well-isolated power supply. However, to build these power supplies requires many large off-chip passive components, and thus the bill of material, the package pin count, and the printed circuit board area and complexity increase dramatically, leading to higher overall cost. Conventional (single-frequency) Single-Inductor Multiple-Output (SIMO) power converter topology can be employed to reduce the burden of off-chip inductors while producing a large number of outputs. However, this strategy requires even larger off-chip output capacitors than single-output converters due to time multiplexing between the multiple outputs, and thus many of them suffer from cross coupling issues that limit the isolation between the outputs. In this thesis, a Dual-Frequency SIMO (DF-SIMO) buck converter topology is proposed. Unlike conventional SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency (~2 MHz) simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V, while switching the output stage at higher frequency enables faster output dynamic response, better cross-regulation, and smaller output capacitors without the efficiency and design complexity penalty of switching both the input and output stages at high frequency. Moreover, for output switching frequency higher than 100 MHz, the output capacitors can be small enough to be integrated on-chip. A 5-output 2-MHz/120-MHz design in 45-nm CMOS with 1.8-V input targeting low-power microcontrollers is presented as an application. The outputs vary from 0.6 to 1.6 V, with 4 outputs providing up to 15 mA and one output providing up to 50 mA. The design uses single 10-uH off-chip inductor, 2-nF on-chip capacitor for each 15-mA output and 4.5-nF for the 50-mA output. The peak efficiency is 73%, Dynamic Voltage Scaling (DVS) is 0.6 V/80 ns, and settling time is 30 ns for half-to-full load steps with no observable overshoot/undershoot or cross-coupling transients. The DF-SIMO topology enables realizing multiple efficient power supplies with faster dynamic response, better cross-regulation, and lower overall cost compared to conventional SIMO topologies

A very fast control based on hysteresis of the Cout current with a frequency loop to operate at constant frequency

The combination of non-linear control and linear control proposed in [1] provides very fast transient response (voltage step from 1 V to 1.5 V in 2 μs). This non-linear control is based on hysteretic control of the Cout current. This system is very sensitive to effects like aging, temperature, input and output voltage variation, etc., that modify the switching frequency. This paper proposes a frequency loop to avoid the frequency variation and to adjust the switching frequency to the nominal value by changing the hysteretic band. The design and analysis of the nonlinear loop, the voltage loop and frequency loop are presented in detail with a design example. A 5 MHz buck converter is developed and experimental results validate the loops design, obtaining the same fast transient response (from 1.5 V to 2.5 V in 2 μs) but keeping constant the switching frequency in steady state