Reversible computation, quantum computation, and computer architectures in between

Thanks to the cosine-sine decomposition of unitary matrices, an arbitrary quantum circuit, acting on w qubits, can be decomposed into 2^w-1 elementary quantum gates, called controlled V gates. Thanks to the Birkhoff decomposition of doubly stochastic matrices, an arbitrary (classical) reversible circuit, acting on w bits, can be decomposed into 2w-1 elementary gates, called controlled NOT gates. The question arises under which conditions these two synthesis methods are applicable for intermediate cases, i.e. computers based on some group, which simultaneously is a subgroup of the unitary group U(2^w) and a supergroup of the symmetric group S_{2^w}. It turns out that many groups either belong to a class that might have a cosine-sine-like decomposition but no Birkhoff-like decomposition and a second class that might have both decompositions. For an arbitrary group, in order to find out to which class it belongs, it suffices to evaluate a function Phi(m), deduced either from its order (in case of a finite group) or from its dimension (in case of a Lie group). Here m=2^w is the degree of the group

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams

Reversible logic synthesis is an emerging research area to aid the circuit implementation for multiple nano-scale technologies with bounded fan-out. Due to the inherent com- plexity of this problem, several heuristics are proposed in the literature. Among those, reversible logic synthesis using decision diagrams offers an attractive solution due to its scalability and performance. In this paper, we exploit a novel, canonical, Bicon- ditional Binary Decision Diagram (BBDD) for reversible logic synthesis. Using BBDD, for multiple classes of Boolean functions, superior circuit performance is achievable due to its compact representation. We discuss theoretical and experimental studies in comparison with state-of-the-art reversible logic synthesis based on decision diagrams

HDL-based Synthesis of Reversible Circuits : A Scalable Design Approach

Reversible computing is a promising research field due to its applications in several emerging technologies. Accordingly, several approaches for the design of reversible circuits have been introduced. Hardware Description Languages approach scales better than other methodologies, however, its main drawback is substantial amounts of additional circuit lines. This dissertation is an important step towards an elaborated scalable design flow of reversible circuits. In which, HDL-based design of reversible circuit is optimised, with line-awareness considered as the main objective. A line-aware programming style for a dedicated reversible hardware description language SyReC is proposed. Another contribution is a line-aware computation of HDL expressions. Reversible circuits' synthesis from a conventional hardware description language (VHDL) is examined. Finally, syntactical extensions to the dedicated hardware description language SyReC are suggested