Concatenated Turbo/LDPC codes for deep space communications: performance and implementation

Deep space communications require error correction codes able to reach extremely low bit-error-rates, possibly with a steep waterfall region and without error floor. Several schemes have been proposed in the literature to achieve these goals. Most of them rely on the concatenation of different codes that leads to high hardware implementation complexity and poor resource sharing. This work proposes a scheme based on the concatenation of non-custom LDPC and turbo codes that achieves excellent error correction performance. Moreover, since both LDPC and turbo codes can be decoded with the BCJR algorithm, our preliminary results show that an efficient hardware architecture with high resource reuse can be designe

Perturbed Adaptive Belief Propagation Decoding for High-Density Parity-Check Codes

Algebraic codes such as BCH code are receiving renewed interest as their short block lengths and low/no error floors make them attractive for ultra-reliable low-latency communications (URLLC) in 5G wireless networks. This article aims at enhancing the traditional adaptive belief propagation (ABP) decoding, which is a soft-in-soft-out (SISO) decoding for high-density parity-check (HDPC) algebraic codes, such as Reed-Solomon (RS) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and product codes. The key idea of traditional ABP is to sparsify certain columns of the parity-check matrix corresponding to the least reliable bits with small log-likelihood-ratio (LLR) values. This sparsification strategy may not be optimal when some bits have large LLR magnitudes but wrong signs. Motivated by this observation, we propose a Perturbed ABP (P-ABP) to incorporate a small number of unstable bits with large LLRs into the sparsification operation of the parity-check matrix. In addition, we propose to apply partial layered scheduling or hybrid dynamic scheduling to further enhance the performance of P-ABP. Simulation results show that our proposed decoding algorithms lead to improved error correction performances and faster convergence rates than the prior-art ABP variants

Mutual Information-Maximizing Quantized Belief Propagation Decoding of Regular LDPC Codes

In mutual information-maximizing lookup table (MIM-LUT) decoding of low-density parity-check (LDPC) codes, table lookup operations are used to replace arithmetic operations. In practice, large tables need to be decomposed into small tables to save the memory consumption, at the cost of degraded error performance. In this paper, we propose a method, called mutual information-maximizing quantized belief propagation (MIM-QBP) decoding, to remove the lookup tables used for MIM-LUT decoding. Our method leads to a very efficient decoder, namely the MIM-QBP decoder, which can be implemented based only on simple mappings and fixed-point additions. Simulation results show that the MIM-QBP decoder can always considerably outperform the state-of-the-art MIM-LUT decoder, mainly because it can avoid the performance loss due to table decomposition. Furthermore, the MIM-QBP decoder with only 3 bits per message can outperform the floating-point belief propagation (BP) decoder at high signal-to-noise ratio (SNR) regions when testing on high-rate codes with a maximum of 10-30 iterations

A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

This paper propose a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than $10^{-13}$ at a bit-energy-to-noise-power-spectral-density ratio ($E_b/N_0$) of 3.55 dB.Comment: accepted to IEEE Transactions on Circuits and Systems

낸드플래시 메모리 오류정정을 위한 고성능 LDPC 복호방법 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 성원용.반도체 공정의 미세화에 따라 비트 에러율이 증가하는 낸드 플래시 메모리에서 고성능 에러 정정 방법은 필수적이다. Low-density parity-check (LDPC) 부호와 같은 연판정 에러 정정 부호는 뛰어난 에러 정정 성능을 보이지만, 높은 구현 복잡도로 인해 플래시 메모리 시스템에 적용되기 힘든 단점이 있다. 본 논문에서는 LDPC 부호의 효율적인 복호를 위해 고성능 메시지 전파 스케줄링 방법과 저 복잡도 복호 알고리즘을 제안한다. 특히 finite geometry (FG) LDPC 부호에 대한 효율적인 디코더 아키텍쳐를 제안하며, 구현된 디코더를 이용하여 낸드 플래시 메모리에 대해 연판정 복호시의 에너지 소모량에 대해 연구한다. 본 논문의 첫 번째 부분에서는 동적 스케줄링 (informed dynamic scheduling, IDS) 알고리즘의 성능향상 방법에 대해 연구한다. 이를 위해 우선 기존의 가장 빠른 수렴 속도를 보이는 IDS 알고리즘인 레지듀얼 신뢰 전파 (residual belief propagation, RBP) 알고리즘의 동작 특성을 분석하고, 이를 바탕으로 특정 노드에 메시지 갱신이 집중되는 것을 방지하여 RBP 알고리즘의 수렴속도를 증가시킨 improved RBP (iRBP) 알고리즘을 제안한다. 또한 iRBP의 뛰어난 수렴속도와 기존의 NS 알고리즘의 우수한 에러 정정 능력을 모두 갖춘 신드롬 기반의 혼합 스케줄링 (mixed scheduling) 방법을 제안한다. 끝으로 다양한 부호율의 LDPC 부호에 대한 모의실험을 통해 제안된 신드롬 기반의 혼합 스케줄링 방법이 본 논문에서 시험된 다른 모든 스케줄링 알고리즘의 성능을 능가함을 확인하였다. 논문의 두 번째 부분에서는 복호 실패시 많은 비트 에러를 발생시키는 a posteriori probability (APP) 알고리즘의 개선 방안에 방안을 제안한다. 또한 빠른 수렴속도와 우수한 에러 마루 (error-floor) 성능으로 데이터 저장장치에 적합한 FG-LDPC 부호에 대해 제안된 알고리즘이 적용된 하드웨어 아키텍처를 제안하였다. 제안된 아키텍처는 높은 노드 가중치를 가지는 FG-LDPC 부호에 적합하도록 쉬프트 레지스터 (shift registers)와 SRAM 기반의 혼합 구조를 채용하며, 높은 처리량을 얻기 위해 파이프라인된 병렬 아키텍처를 사용한다. 또한 메모리 사용량을 줄이기 위해 세 가지의 메모리 용량 감소 기법을 적용하며, 전력 소비를 줄이기 위해 두 가지의 저전력 기법을 제안한다. 본 제안된 아키텍처는 부호율 0.96의 (68254, 65536) Euclidean geometry LDPC 부호에 대해 0.13-um CMOS 공정에서 구현하였다. 마지막으로 본 논문에서는 연판정 복호가 적용된 낸드 플래시 메모리 시스템의 에너지 소모를 낮추는 방법에 대해 제안한다. 연판정 기반의 에러 정정 알고리즘은 높은 성능을 보이지만, 이는 플래시 메모리의 센싱 수와 에너지 소모를 증가 시키는 단점이 있다. 본 연구에서는 앞서 구현된 LDPC 디코더가 채용된 낸드 플래시 메모리 시스템의 에너지 소모를 분석하고, LDPC 디코더와 BCH 디코더 간의 칩 사이즈와 에너지 소모량을 비교하였다. 이와 더불어 본 논문에서는 LDPC 디코더를 이용한 센싱 정밀도 결정 방법을 제안한다. 본 연구를 통해 제안된 복호 및 스케줄링 알고리즘, VLSI 아키텍쳐, 그리고 읽기 정밀도 결정 방법을 통해 낸드 플래시 메모리 시스템의 에러 정정 성능을 극대화 하고 에너지 소모를 최소화 할 수 있다.High-performance error correction for NAND flash memory is greatly needed because the raw bit error rate increases as the semiconductor geometry shrinks for high density. Soft-decision error correction, such as low-density parity-check (LDPC) codes, offers high performance but their implementation complexity hinders wide adoption to consumer products. This dissertation proposes two high-performance message-passing schedules and a low-complexity decoding algorithm for LDPC codes. In particular, an efficient decoder architecture for finite geometry (FG) LDPC codes is proposed, and the energy consumption of soft-decision decoding for NAND flash memory is analyzed. The first part of this dissertation is devoted to improving the informed dynamic scheduling (IDS) algorithms. We analyze the behavior of the residual belief propagation (RBP), which is the fastest IDS algorithm, and develop an improved RBP (iRBP) by avoiding the concentration of message updates at a particular node. We also study the syndrome-based mixed scheduling of the iRBP and the node-wise scheduling (NS). The proposed mixed scheduling outperforms all other scheduling methods tested in this work. The next part of this dissertation is to develop a conditional variable node update scheme for the a posteriori probability (APP) algorithm. The developed algorithm is robust to decoding failures and can reduce the dynamic power consumption by lowering switching activities in the LDPC decoder. To implement the developed algorithm, we propose a memory-efficient pipelined parallel architecture for LDPC decoding. The architecture employs FG-LDPC codes that not only show fast convergence speed and good error-floor performance but also perform well with iterative decoding algorithms, which is especially suitable for data storage devices. We also developed a rate-0.96 (68254, 65536) Euclidean geometry LDPC code and implemented the proposed architecture in 0.13-um CMOS technology. This dissertation also covers low-energy error correction of NAND flash memory through soft-decision decoding. The soft-decision-based error correction algorithms show high performance, but they demand an increased number of flash memory sensing operations and consume more energy for memory access. We examine the energy consumption of a NAND flash memory system equipping an LDPC code-based soft-decision error correction circuit. The sum of energy consumed at NAND flash memory and the LDPC decoder is minimized. In addition, the chip size and energy consumption of the decoder were compared with those of two Bose-Chaudhuri-Hocquenghem (BCH) decoding circuits showing the comparable error performance and the throughput. We also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. This dissertation is intended to develop high-performance and low-power error correction circuits for NAND flash memory by studying improved decoding and scheduling algorithms, VLSI architecture, and a read precision selection method.1 Introduction 1 1.1 NAND Flash Memory 1 1.2 LDPC Codes 4 1.3 Outline of the Dissertation 6 2 LDPC Decoding and Scheduling Algorithms 8 2.1 Introduction 8 2.2 Decoding Algorithms for LDPC Codes 10 2.2.1 Belief Propagation Algorithm 10 2.2.2 Simplified Belief Propagation Algorithms 12 2.3 Message-Passing Schedules for Decoding of LDPC Codes 15 2.3.1 Static Schedules 15 2.3.2 Dynamic Schedules 17 3 Improved Dynamic Scheduling Algorithms for Decoding of LDPC Codes 22 3.1 Introduction 22 3.2 Improved Residual Belief Propagation Algorithm 23 3.3 Syndrome-Based Mixed Scheduling of iRBP and NS 26 3.4 Complexity Analysis and Simulation Results 28 3.4.1 Complexity Analysis 28 3.4.2 Simulation Results 29 3.5 Concluding Remarks 33 4 A Pipelined Parallel Architecture for Decoding of Finite-Geometry LDPC Codes 36 4.1 Introduction 36 4.2 Finite-Geometry LDPC Codes and Conditional Variable Node Update Algorithm 38 4.2.1 Finite-Geometry LDPC codes 38 4.2.2 Conditional Variable Node Update Algorithm for Fixed-Point Normalized APP-Based Algorithm 40 4.3 Decoder Architecture 46 4.3.1 Baseline Sequential Architecture 46 4.3.2 Pipelined-Parallel Architecture 54 4.3.3 Memory Capacity Reduction 57 4.4 Implementation Results 60 4.5 Concluding Remarks 64 5 Low-Energy Error Correction of NAND Flash Memory through Soft-Decision Decoding 66 5.1 Introduction 66 5.2 Energy Consumption of Read Operations in NAND Flash Memory 67 5.2.1 Voltage Sensing Scheme for Soft-Decision Data Output 67 5.2.2 LSB and MSB Concurrent Access Scheme for Low-Energy Soft-Decision Data Output 72 5.2.3 Energy Consumption of Read Operations in NAND Flash Memory 73 5.3 The Performance of Soft-Decision Error Correction over a NAND Flash Memory Channel 76 5.4 Hardware Performance of the (68254, 65536) LDPC Decoder 81 5.4.1 Energy Consumption of the LDPC Decoder 81 5.4.2 Performance Comparison of the LDPC Decoder and Two BCH Decoders 83 5.5 Low-Energy Error Correction Scheme for NAND Flash Memory 87 5.5.1 Optimum Precision for Low-Energy Decoding 87 5.5.2 Iteration Count-Based Precision Selection 90 5.6 Concluding Remarks 91 6 Conclusion 94 Bibliography 96 Abstract in Korean 110 감사의 글 112Docto

Analysis and optimization of the satellite-to-plane link of an aeronautical global system

En aquest projecte s'ha analitzat i optimitzat l'enllaç satèl·lit amb avió per a un sistema aeronàutic global. Aquest nou sistema anomenat ANTARES està dissenyat per a comunicar avions amb estacions base mitjançant un satèl·lit. Aquesta és una iniciativa on hi participen institucions oficials en l'aviació com ara l'ECAC i que és desenvolupat en una col·laboració europea d'universitats i empreses. El treball dut a terme en el projecte compren bàsicament tres aspectes. El disseny i anàlisi de la gestió de recursos. La idoneïtat d'utilitzar correcció d'errors en la capa d'enllaç i en cas que sigui necessària dissenyar una opció de codificació preliminar. Finalment, estudiar i analitzar l'efecte de la interferència co-canal en sistemes multifeix. Tots aquests temes són considerats només per al "forward link". L'estructura que segueix el projecte és primer presentar les característiques globals del sistema, després centrar-se i analitzar els temes mencionats per a poder donar resultats i extreure conclusions.En este proyecto se ha analizado y optimizado el enlace satélite a avión para un sistema aeronáutico global. Este nuevo sistema, ANTARES, está diseñado para comunicar aviones y estaciones base mediante un satélite. Esta es una iniciativa europea en la que participan varias instituciones oficiales en aviación como el ECAC y es desarrollada en una colaboración europea de universidades y empresas. El trabajo llevado a cabo en este proyecto comprende básicamente tres aspectos. El diseño y análisis de la gestión de recursos. La idoneidad de usar corrección de errores en la capa de enlace y en caso que sea necesario diseñar una opción de codificación preliminar. Finalmente, estudiar y analizar el efecto de la interferencia co-canal en sistemas multihaz. Todos estos temas se consideran sólo en el "forward link". La estructura que sigue el trabajo es, primero presentar las características globales del sistema, luego centrarse y analizar los temas mencionados para finalmente dar resultados y extraer conclusiones.In this project it is analyzed and optimized the satellite-to-plane link of an aeronautical global system. This new upcoming system called ANTARES is intended for communicating airplanes and ground stations through a satellite system. This is a European initiative involving official institutions in terms of aviation such as the ECAC and developed in a European collaboration of universities and companies. The work carried out in the project comprehends basically three issues. The Radio Resource Management analysis and design. Analyze the suitability of using Link Layer-Forward Error Correction in the system and in case it is necessary design a preliminary coding option. Finally, study and analyze the effect of the co-channel interference in multibeam systems. All these issues are considered only for the forward link of the system. The structure of the project is as follows, first present the global characteristics of the system, then focus and analyze the mentioned subjects and finally give results and take conclusions on the work

A tutorial on the characterisation and modelling of low layer functional splits for flexible radio access networks in 5G and beyond

The centralization of baseband (BB) functions in a radio access network (RAN) towards data processing centres is receiving increasing interest as it enables the exploitation of resource pooling and statistical multiplexing gains among multiple cells, facilitates the introduction of collaborative techniques for different functions (e.g., interference coordination), and more efficiently handles the complex requirements of advanced features of the fifth generation (5G) new radio (NR) physical layer, such as the use of massive multiple input multiple output (MIMO). However, deciding the functional split (i.e., which BB functions are kept close to the radio units and which BB functions are centralized) embraces a trade-off between the centralization benefits and the fronthaul costs for carrying data between distributed antennas and data processing centres. Substantial research efforts have been made in standardization fora, research projects and studies to resolve this trade-off, which becomes more complicated when the choice of functional splits is dynamically achieved depending on the current conditions in the RAN. This paper presents a comprehensive tutorial on the characterisation, modelling and assessment of functional splits in a flexible RAN to establish a solid basis for the future development of algorithmic solutions of dynamic functional split optimisation in 5G and beyond systems. First, the paper explores the functional split approaches considered by different industrial fora, analysing their equivalences and differences in terminology. Second, the paper presents a harmonized analysis of the different BB functions at the physical layer and associated algorithmic solutions presented in the literature, assessing both the computational complexity and the associated performance. Based on this analysis, the paper presents a model for assessing the computational requirements and fronthaul bandwidth requirements of different functional splits. Last, the model is used to derive illustrative results that identify the major trade-offs that arise when selecting a functional split and the key elements that impact the requirements.This work has been partially funded by Huawei Technologies. Work by X. Gelabert and B. Klaiqi is partially funded by the European Union's Horizon Europe research and innovation programme (HORIZON-MSCA-2021-DN-0) under the Marie Skłodowska-Curie grant agreement No 101073265. Work by J. Perez-Romero and O. Sallent is also partially funded by the Smart Networks and Services Joint Undertaking (SNS JU) under the European Union’s Horizon Europe research and innovation programme under Grant Agreements No. 101096034 (VERGE project) and No. 101097083 (BeGREEN project) and by the Spanish Ministry of Science and Innovation MCIN/AEI/10.13039/501100011033 under ARTIST project (ref. PID2020-115104RB-I00). This last project has also funded the work by D. Campoy.Peer ReviewedPostprint (author's final draft

Joint source-channel-network coding in wireless mesh networks with temporal reuse

Technological innovation that empowers tiny low-cost transceivers to operate with a high degree of utilisation efficiency in multihop wireless mesh networks is contributed in this dissertation. Transmission scheduling and joint source-channel-network coding are two of the main aspects that are addressed. This work focuses on integrating recent enhancements such as wireless network coding and temporal reuse into a cross-layer optimisation framework, and to design a joint coding scheme that allows for space-optimal transceiver implementations. Link-assigned transmission schedules with timeslot reuse by multiple links in both the space and time domains are investigated for quasi-stationary multihop wireless mesh networks with both rate and power adaptivity. Specifically, predefined cross-layer optimised schedules with proportionally fair end-to-end flow rates and network coding capability are constructed for networks operating under the physical interference model with single-path minimum hop routing. Extending transmission rights in a link-assigned schedule allows for network coding and temporal reuse, which increases timeslot usage efficiency when a scheduled link experiences packet depletion. The schedules that suffer from packet depletion are characterised and a generic temporal reuse-aware achievable rate region is derived. Extensive computational experiments show improved schedule capacity, quality of service, power efficiency and benefit from opportunistic bidirectional network coding accrued with schedules optimised in the proposed temporal reuse-aware convex capacity region. The application of joint source-channel coding, based on fountain codes, in the broadcast timeslot of wireless two-way network coding is also investigated. A computationally efficient subroutine is contributed to the implementation of the fountain compressor, and an error analysis is done. Motivated to develop a true joint source-channel-network code that compresses, adds robustness against channel noise and network codes two packets on a single bipartite graph and iteratively decodes the intended packet on the same Tanner graph, an adaptation of the fountain compressor is presented. The proposed code is shown to outperform a separated joint source-channel and network code in high source entropy and high channel noise regions, in anticipated support of dense networks that employ intelligent signalling. AFRIKAANS : Tegnologiese innovasie wat klein lae-koste kommunikasie toestelle bemagtig om met ’n hoë mate van benuttings doeltreffendheid te werk word bygedra in hierdie proefskrif. Transmissie-skedulering en gesamentlike bron-kanaal-netwerk kodering is twee van die belangrike aspekte wat aangespreek word. Hierdie werk fokus op die integrasie van onlangse verbeteringe soos draadlose netwerk kodering en temporêre herwinning in ’n tussen-laag optimaliserings raamwerk, en om ’n gesamentlike kodering skema te ontwerp wat voorsiening maak vir spasie-optimale toestel implementerings. Skakel-toegekende transmissie skedules met tydgleuf herwinning deur veelvuldige skakels in beide die ruimte en tyd domeine word ondersoek vir kwasi-stilstaande, veelvuldige-sprong draadlose rooster netwerke met beide transmissie-spoed en krag aanpassings. Om spesifiek te wees, word vooraf bepaalde tussen-laag geoptimiseerde skedules met verhoudings-regverdige punt-tot-punt vloei tempo’s en netwerk kodering vermoë saamgestel vir netwerke wat bedryf word onder die fisiese inmengings-model met enkel-pad minimale sprong roetering. Die uitbreiding van transmissie-regte in ’n skakel-toegekende skedule maak voorsiening vir netwerk kodering en temporêre herwinning, wat tydgleuf gebruiks-doeltreffendheid verhoog wanneer ’n geskeduleerde skakel pakkie-uitputting ervaar. Die skedules wat ly aan pakkie-uitputting word gekenmerk en ’n generiese temporêre herwinnings-bewuste haalbare transmissie-spoed gebied word afgelei. Omvattende berekenings-eksperimente toon verbeterde skedulerings kapasiteit, diensgehalte, krag doeltreffendheid asook verbeterde voordeel wat getrek word uit opportunistiese tweerigting netwerk kodering met die skedules wat geoptimiseer word in die temporêre herwinnings-bewuste konvekse transmissie-spoed gebied. Die toepassing van gesamentlike bron-kanaal kodering, gebaseer op fontein kodes, in die uitsaai-tydgleuf van draadlose tweerigting netwerk kodering word ook ondersoek. ’n Berekenings-effektiewe subroetine word bygedra in die implementering van die fontein kompressor, en ’n foutanalise word gedoen. Gemotiveer om ’n ware gesamentlike bron-kanaal-netwerk kode te ontwikkel, wat robuustheid byvoeg teen kanaal geraas en twee pakkies netwerk kodeer op ’n enkele bipartiete grafiek en die beoogde pakkie iteratief dekodeer op dieselfde Tanner grafiek, word ’n aanpassing van die fontein kompressor aangebied. Dit word getoon dat die voorgestelde kode ’n geskeide gesamentlike bron-kanaal en netwerk kode in hoë bron-entropie en ho¨e kanaal-geraas gebiede oortref in verwagte ondersteuning van digte netwerke wat van intelligente sein-metodes gebruik maak.Dissertation (MEng)--University of Pretoria, 2011.Electrical, Electronic and Computer Engineeringunrestricte