The ARIEL Instrument Control Unit design for the M4 Mission Selection Review of the ESA's Cosmic Vision Program

The Atmospheric Remote-sensing Infrared Exoplanet Large-survey mission (ARIEL) is one of the three present candidates for the ESA M4 (the fourth medium mission) launch opportunity. The proposed Payload will perform a large unbiased spectroscopic survey from space concerning the nature of exoplanets atmospheres and their interiors to determine the key factors affecting the formation and evolution of planetary systems. ARIEL will observe a large number (>500) of warm and hot transiting gas giants, Neptunes and super-Earths around a wide range of host star types, targeting planets hotter than 600 K to take advantage of their well-mixed atmospheres. It will exploit primary and secondary transits spectroscopy in the 1.2-8 um spectral range and broad-band photometry in the optical and Near IR (NIR). The main instrument of the ARIEL Payload is the IR Spectrometer (AIRS) providing low-resolution spectroscopy in two IR channels: Channel 0 (CH0) for the 1.95-3.90 um band and Channel 1 (CH1) for the 3.90-7.80 um range. It is located at the intermediate focal plane of the telescope and common optical system and it hosts two IR sensors and two cold front-end electronics (CFEE) for detectors readout, a well defined process calibrated for the selected target brightness and driven by the Payload's Instrument Control Unit (ICU).Comment: Experimental Astronomy, Special Issue on ARIEL, (2017

Fast Hardware Implementations of Static P Systems

In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as words of some regular context-free language. Then, using formal power series it is possible to obtain the number of possibilities and select one of them following a uniform distribution, in a fair and non-deterministic way. According to these ideas, we yield an implementation whose results show an important speed-up, with a strong independence from the size of the P system.Ministry of Science and Innovation of the Spanish Government under the project TEC2011-27936 (HIPERSYS)European Regional Development Fund (ERDF)Ministry of Education of Spain (FPU grant AP2009-3625)ANR project SynBioTI

The Open Network Laboratory (a resource for high performance networking research)

The Open Network Laboratory (ONL) is a remotely accessible network testbed designed to enable network researchers to conduct experiments using high performance routers and applications. ONL™s Remote Laboratory Interface (RLI) allows users to easily configure a network topology, initialize and modify the routers™ routing tables, packet classification tables and queuing parameters. It also enables users to add software plugins to the embedded processors available at each of the routers™ ports, enabling the introduction of new functionality. The routers provide a large number of built-in counters to track various aspects of system usage, and the RLI software makes these available through easy-to-use real-time charts. This allows researchers to expose what is happening fiunder the surfacefl enabling them to develop the insights needed to understand system behavior in complex situations and to deliver compelling demonstrations of their ideas in a realistic operating environment. This paper provides an overview of ONL, emphasizing how it can be used to carry out a wide range of networking experiments

Use of Field Programmable Gate Array Technology in Future Space Avionics

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA

Field Programmable Port Extender (FPX) User Guide (Version 2.2)

This manual summarizes how to insert the Field Programmable Port Extender (FPX) into the Washington University Gigabit Switch (WUGS), how to install the NCHARGE control software, how to initialize the system, and how to reprogram a user-defined module into the FPX over the network using the included web-based tools

Mechanical transistors for logic-with-memory computing

As a potential revolutionary topic in future information processing, mechanical computing has gained tremendous attention for replacing or supplementing conventional electronics vulnerable to power outages, security attacks, and harsh environments. Despite its potential for constructing intelligent matter towards nonclassical computing systems beyond the von Neumann architecture, most works on mechanical computing demonstrated that the ad hoc design of simple logic gates cannot fully realize a universal mechanical processing framework involving interconnected arithmetic logic components and memory. However, such a logic-with-memory computing architecture is critical for complex and persistent state-dependent computations such as sequential logic. Here we propose a mechanical transistor (M-Transistor), abstracting omnipresent temperatures as the input-output mechanical bits, which consists of a metamaterial thermal channel as the gate terminal driving a nonlinear bistable soft actuator to selectively connect the output terminal to two other variable thermal sources. This M-Transistor is an elementary unit to modularly form various combinational and sequential circuits, such as complex logic gates, registers (volatile memory), and long-term memories (non-volatile memory) with much fewer units than the electronic counterparts. Moreover, they can establish a universal processing core comprising an arithmetic circuit and a register in a compact, reprogrammable network involving periodic read, write, memory, and logic operations of the mechanical bits. Our work contributes to realizing a non-electric universal mechanical computing architecture that combines multidisciplinary engineering with structural mechanics, materials science, thermal engineering, physical intelligence, and computational science.Comment: 25 pages, 4 figures, Articl